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peteralieb |
//-----------------------------------------------------------------------------
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// Title : Virtex-4 Ethernet MAC Local Link Wrapper
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// Project : Virtex-4 Embedded Tri-Mode Ethernet MAC Wrapper
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// File : v4_emac_v4_8_locallink.v
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// Version : 4.8
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//-----------------------------------------------------------------------------
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//
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// (c) Copyright 2004-2010 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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//-----------------------------------------------------------------------------
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// Description: This level:
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//
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// * instantiates the TEMAC top level file (the TEMAC
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// wrapper with the clocking and physical interface
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// logic;
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//
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// * instantiates TX and RX reference design FIFO's with
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// a local link interface.
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//
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// Please refer to the Datasheet, Getting Started Guide, and
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// the Virtex-4 Embedded Tri-Mode Ethernet MAC User Gude for
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// further information.
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//-----------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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//-----------------------------------------------------------------------------
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// The module declaration for the MAC with FIFO design.
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//-----------------------------------------------------------------------------
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module v4_emac_v4_8_locallink
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(
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// Local link Receiver Interface - EMAC0
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RX_LL_CLOCK_0,
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RX_LL_RESET_0,
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RX_LL_DATA_0,
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RX_LL_SOF_N_0,
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RX_LL_EOF_N_0,
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RX_LL_SRC_RDY_N_0,
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RX_LL_DST_RDY_N_0,
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RX_LL_FIFO_STATUS_0,
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// Local link Transmitter Interface - EMAC0
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TX_LL_CLOCK_0,
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TX_LL_RESET_0,
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TX_LL_DATA_0,
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TX_LL_SOF_N_0,
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TX_LL_EOF_N_0,
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TX_LL_SRC_RDY_N_0,
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TX_LL_DST_RDY_N_0,
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// Client Receiver Interface - EMAC0
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EMAC0CLIENTRXDVLD,
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EMAC0CLIENTRXFRAMEDROP,
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EMAC0CLIENTRXSTATS,
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EMAC0CLIENTRXSTATSVLD,
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EMAC0CLIENTRXSTATSBYTEVLD,
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// Client Transmitter Interface - EMAC0
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CLIENTEMAC0TXIFGDELAY,
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EMAC0CLIENTTXSTATS,
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EMAC0CLIENTTXSTATSVLD,
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EMAC0CLIENTTXSTATSBYTEVLD,
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// MAC Control Interface - EMAC0
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CLIENTEMAC0PAUSEREQ,
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CLIENTEMAC0PAUSEVAL,
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RX_CLIENT_CLK_0,
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TX_CLIENT_CLK_0,
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// MII Interface - EMAC0
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MII_COL_0,
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MII_CRS_0,
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MII_TXD_0,
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MII_TX_EN_0,
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MII_TX_ER_0,
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MII_TX_CLK_0,
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MII_RXD_0,
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MII_RX_DV_0,
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MII_RX_ER_0,
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MII_RX_CLK_0,
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// Preserved Tie-Off Pins for EMAC0
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SPEED_VECTOR_IN_0,
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HOSTCLK,
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// Asynchronous Reset
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RESET
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);
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//-----------------------------------------------------------------------------
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// Port Declarations
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//-----------------------------------------------------------------------------
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// Local link Receiver Interface - EMAC0
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input RX_LL_CLOCK_0;
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input RX_LL_RESET_0;
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output [7:0] RX_LL_DATA_0;
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output RX_LL_SOF_N_0;
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output RX_LL_EOF_N_0;
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output RX_LL_SRC_RDY_N_0;
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input RX_LL_DST_RDY_N_0;
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output [3:0] RX_LL_FIFO_STATUS_0;
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// Local link Transmitter Interface - EMAC0
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input TX_LL_CLOCK_0;
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input TX_LL_RESET_0;
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input [7:0] TX_LL_DATA_0;
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input TX_LL_SOF_N_0;
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input TX_LL_EOF_N_0;
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input TX_LL_SRC_RDY_N_0;
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output TX_LL_DST_RDY_N_0;
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// Client Receiver Interface - EMAC0
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output EMAC0CLIENTRXDVLD;
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output EMAC0CLIENTRXFRAMEDROP;
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output [6:0] EMAC0CLIENTRXSTATS;
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output EMAC0CLIENTRXSTATSVLD;
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output EMAC0CLIENTRXSTATSBYTEVLD;
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// Client Transmitter Interface - EMAC0
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input [7:0] CLIENTEMAC0TXIFGDELAY;
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output EMAC0CLIENTTXSTATS;
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output EMAC0CLIENTTXSTATSVLD;
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output EMAC0CLIENTTXSTATSBYTEVLD;
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// MAC Control Interface - EMAC0
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input CLIENTEMAC0PAUSEREQ;
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input [15:0] CLIENTEMAC0PAUSEVAL;
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output RX_CLIENT_CLK_0;
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output TX_CLIENT_CLK_0;
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// MII Interface - EMAC0
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input MII_COL_0;
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input MII_CRS_0;
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output [3:0] MII_TXD_0;
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output MII_TX_EN_0;
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output MII_TX_ER_0;
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input MII_TX_CLK_0;
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input [3:0] MII_RXD_0;
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input MII_RX_DV_0;
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input MII_RX_ER_0;
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input MII_RX_CLK_0;
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// Preserved Tie-Off Pins for EMAC0
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input [1:0] SPEED_VECTOR_IN_0;
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input HOSTCLK;
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// Asynchronous Reset
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input RESET;
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//-----------------------------------------------------------------------------
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// Wire and Reg Declarations
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//-----------------------------------------------------------------------------
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// Global asynchronous reset
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wire reset_i;
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// Client interface clocking signals - EMAC0
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wire tx_clk_0_i;
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wire rx_clk_0_i;
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// Internal client interface connections - EMAC0
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// Transmitter interface
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wire [7:0] tx_data_0_i;
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wire tx_data_valid_0_i;
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wire tx_underrun_0_i;
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wire tx_ack_0_i;
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wire tx_collision_0_i;
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wire tx_retransmit_0_i;
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// Receiver interface
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wire [7:0] rx_data_0_i;
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wire rx_data_valid_0_i;
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wire rx_good_frame_0_i;
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wire rx_bad_frame_0_i;
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// Registers for the EMAC receiver output
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reg [7:0] rx_data_0_r;
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reg rx_data_valid_0_r;
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reg rx_good_frame_0_r;
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reg rx_bad_frame_0_r;
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// create a synchronous reset in the transmitter clock domain
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reg [5:0] tx_pre_reset_0_i;
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reg tx_reset_0_i;
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// create a synchronous reset in the receiver clock domain
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reg [5:0] rx_pre_reset_0_i;
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reg rx_reset_0_i;
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// synthesis attribute ASYNC_REG of rx_pre_reset_0_i is "TRUE";
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// synthesis attribute ASYNC_REG of tx_pre_reset_0_i is "TRUE";
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//synthesis attribute keep of tx_data_0_i is "true";
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//synthesis attribute keep of tx_data_valid_0_i is "true";
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//synthesis attribute keep of tx_ack_0_i is "true";
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//synthesis attribute keep of rx_data_0_i is "true";
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//synthesis attribute keep of rx_data_valid_0_i is "true";
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//-----------------------------------------------------------------------------
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// Main Body of Code
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//-----------------------------------------------------------------------------
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// Asynchronous reset input
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assign reset_i = RESET;
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//------------------------------------------------------------------------
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// Instantiate the EMAC Wrapper (v4_emac_v4_8_block.v)
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//------------------------------------------------------------------------
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v4_emac_v4_8_block v4_emac_block_inst
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(
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// Client Receiver Interface - EMAC0
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.RX_CLIENT_CLK_0 (rx_clk_0_i),
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.EMAC0CLIENTRXD (rx_data_0_i),
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.EMAC0CLIENTRXDVLD (rx_data_valid_0_i),
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.EMAC0CLIENTRXGOODFRAME (rx_good_frame_0_i),
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.EMAC0CLIENTRXBADFRAME (rx_bad_frame_0_i),
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.EMAC0CLIENTRXFRAMEDROP (EMAC0CLIENTRXFRAMEDROP),
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.EMAC0CLIENTRXSTATS (EMAC0CLIENTRXSTATS),
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.EMAC0CLIENTRXSTATSVLD (EMAC0CLIENTRXSTATSVLD),
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.EMAC0CLIENTRXSTATSBYTEVLD (EMAC0CLIENTRXSTATSBYTEVLD),
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// Client Transmitter Interface - EMAC0
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.TX_CLIENT_CLK_0 (tx_clk_0_i),
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.CLIENTEMAC0TXD (tx_data_0_i),
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.CLIENTEMAC0TXDVLD (tx_data_valid_0_i),
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.EMAC0CLIENTTXACK (tx_ack_0_i),
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.CLIENTEMAC0TXFIRSTBYTE (1'b0),
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.CLIENTEMAC0TXUNDERRUN (tx_underrun_0_i),
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.EMAC0CLIENTTXCOLLISION (tx_collision_0_i),
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.EMAC0CLIENTTXRETRANSMIT (tx_retransmit_0_i),
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.CLIENTEMAC0TXIFGDELAY (CLIENTEMAC0TXIFGDELAY),
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.EMAC0CLIENTTXSTATS (EMAC0CLIENTTXSTATS),
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.EMAC0CLIENTTXSTATSVLD (EMAC0CLIENTTXSTATSVLD),
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.EMAC0CLIENTTXSTATSBYTEVLD (EMAC0CLIENTTXSTATSBYTEVLD),
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// MAC Control Interface - EMAC0
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.CLIENTEMAC0PAUSEREQ (CLIENTEMAC0PAUSEREQ),
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.CLIENTEMAC0PAUSEVAL (CLIENTEMAC0PAUSEVAL),
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// MII Interface - EMAC0
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.MII_COL_0 (MII_COL_0),
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.MII_CRS_0 (MII_CRS_0),
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.MII_TXD_0 (MII_TXD_0),
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.MII_TX_EN_0 (MII_TX_EN_0),
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.MII_TX_ER_0 (MII_TX_ER_0),
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.MII_TX_CLK_0 (MII_TX_CLK_0),
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.MII_RXD_0 (MII_RXD_0),
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.MII_RX_DV_0 (MII_RX_DV_0),
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.MII_RX_ER_0 (MII_RX_ER_0),
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.MII_RX_CLK_0 (MII_RX_CLK_0),
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// Preserved Tie-Off Pins for EMAC0
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.SPEED_VECTOR_IN_0 (SPEED_VECTOR_IN_0),
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.HOSTCLK (HOSTCLK),
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// Asynchronous Reset Input
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.RESET (reset_i));
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//-------------------------------------------------------------------
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// Instantiate the client side FIFO
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//-------------------------------------------------------------------
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eth_fifo_8 client_side_FIFO_emac0 (
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// EMAC transmitter client interface
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.tx_clk(tx_clk_0_i),
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.tx_reset(tx_reset_0_i),
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.tx_enable(1'b1),
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.tx_data(tx_data_0_i),
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.tx_data_valid(tx_data_valid_0_i),
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.tx_ack(tx_ack_0_i),
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.tx_underrun(tx_underrun_0_i),
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.tx_collision(tx_collision_0_i),
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.tx_retransmit(tx_retransmit_0_i),
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// Transmitter local link interface
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.tx_ll_clock(TX_LL_CLOCK_0),
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.tx_ll_reset(TX_LL_RESET_0),
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.tx_ll_data_in(TX_LL_DATA_0),
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.tx_ll_sof_in_n(TX_LL_SOF_N_0),
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.tx_ll_eof_in_n(TX_LL_EOF_N_0),
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.tx_ll_src_rdy_in_n(TX_LL_SRC_RDY_N_0),
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.tx_ll_dst_rdy_out_n(TX_LL_DST_RDY_N_0),
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.tx_fifo_status(),
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.tx_overflow(),
|
332 |
|
|
|
333 |
|
|
// EMAC receiver client interface
|
334 |
|
|
.rx_clk(rx_clk_0_i),
|
335 |
|
|
.rx_reset(rx_reset_0_i),
|
336 |
|
|
.rx_enable(1'b1),
|
337 |
|
|
.rx_data(rx_data_0_r),
|
338 |
|
|
.rx_data_valid(rx_data_valid_0_r),
|
339 |
|
|
.rx_good_frame(rx_good_frame_0_r),
|
340 |
|
|
.rx_bad_frame(rx_bad_frame_0_r),
|
341 |
|
|
.rx_overflow(),
|
342 |
|
|
|
343 |
|
|
// Receiver local link interface
|
344 |
|
|
.rx_ll_clock(RX_LL_CLOCK_0),
|
345 |
|
|
.rx_ll_reset(RX_LL_RESET_0),
|
346 |
|
|
.rx_ll_data_out(RX_LL_DATA_0),
|
347 |
|
|
.rx_ll_sof_out_n(RX_LL_SOF_N_0),
|
348 |
|
|
.rx_ll_eof_out_n(RX_LL_EOF_N_0),
|
349 |
|
|
.rx_ll_src_rdy_out_n(RX_LL_SRC_RDY_N_0),
|
350 |
|
|
.rx_ll_dst_rdy_in_n(RX_LL_DST_RDY_N_0),
|
351 |
|
|
.rx_fifo_status(RX_LL_FIFO_STATUS_0));
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
//-------------------------------------------------------------------
|
355 |
|
|
// Create synchronous reset signals for use in the FIFO.
|
356 |
|
|
// A synchronous reset signal is created in each
|
357 |
|
|
// clock domain.
|
358 |
|
|
//-------------------------------------------------------------------
|
359 |
|
|
|
360 |
|
|
// Create synchronous reset in the transmitter clock domain.
|
361 |
|
|
always @(posedge tx_clk_0_i, posedge reset_i)
|
362 |
|
|
begin
|
363 |
|
|
if (reset_i === 1'b1)
|
364 |
|
|
begin
|
365 |
|
|
tx_pre_reset_0_i <= 6'h3F;
|
366 |
|
|
tx_reset_0_i <= 1'b1;
|
367 |
|
|
end
|
368 |
|
|
else
|
369 |
|
|
begin
|
370 |
|
|
tx_pre_reset_0_i[0] <= 1'b0;
|
371 |
|
|
tx_pre_reset_0_i[5:1] <= tx_pre_reset_0_i[4:0];
|
372 |
|
|
tx_reset_0_i <= tx_pre_reset_0_i[5];
|
373 |
|
|
end
|
374 |
|
|
end
|
375 |
|
|
|
376 |
|
|
always @(posedge rx_clk_0_i, posedge reset_i)
|
377 |
|
|
begin
|
378 |
|
|
if (reset_i === 1'b1)
|
379 |
|
|
begin
|
380 |
|
|
rx_pre_reset_0_i <= 6'h3F;
|
381 |
|
|
rx_reset_0_i <= 1'b1;
|
382 |
|
|
end
|
383 |
|
|
else
|
384 |
|
|
begin
|
385 |
|
|
rx_pre_reset_0_i[0] <= 1'b0;
|
386 |
|
|
rx_pre_reset_0_i[5:1] <= rx_pre_reset_0_i[4:0];
|
387 |
|
|
rx_reset_0_i <= rx_pre_reset_0_i[5];
|
388 |
|
|
end
|
389 |
|
|
end
|
390 |
|
|
|
391 |
|
|
//--------------------------------------------------------------------
|
392 |
|
|
// Register the receiver outputs from EMAC0 before routing
|
393 |
|
|
// to the FIFO
|
394 |
|
|
//--------------------------------------------------------------------
|
395 |
|
|
always @(posedge rx_clk_0_i, posedge reset_i)
|
396 |
|
|
begin
|
397 |
|
|
if (reset_i == 1'b1)
|
398 |
|
|
begin
|
399 |
|
|
rx_data_valid_0_r <= 1'b0;
|
400 |
|
|
rx_data_0_r <= 8'h00;
|
401 |
|
|
rx_good_frame_0_r <= 1'b0;
|
402 |
|
|
rx_bad_frame_0_r <= 1'b0;
|
403 |
|
|
end
|
404 |
|
|
else
|
405 |
|
|
begin
|
406 |
|
|
rx_data_0_r <= rx_data_0_i;
|
407 |
|
|
rx_data_valid_0_r <= rx_data_valid_0_i;
|
408 |
|
|
rx_good_frame_0_r <= rx_good_frame_0_i;
|
409 |
|
|
rx_bad_frame_0_r <= rx_bad_frame_0_i;
|
410 |
|
|
end
|
411 |
|
|
end
|
412 |
|
|
|
413 |
|
|
// EMAC0 Client outputs to upper levels and user logic
|
414 |
|
|
assign EMAC0CLIENTRXDVLD = rx_data_valid_0_i;
|
415 |
|
|
assign RX_CLIENT_CLK_0 = rx_clk_0_i;
|
416 |
|
|
assign TX_CLIENT_CLK_0 = tx_clk_0_i;
|
417 |
|
|
|
418 |
|
|
endmodule
|