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peteralieb |
//-----------------------------------------------------------------------------
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// Title : Virtex-5 Ethernet MAC Local Link Wrapper
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// Project : Virtex-5 Ethernet MAC Wrappers
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//-----------------------------------------------------------------------------
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// File : v5_emac_v1_6_locallink.v
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//-----------------------------------------------------------------------------
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// Copyright (c) 2004-2008 by Xilinx, Inc. All rights reserved.
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// This text/file contains proprietary, confidential
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// information of Xilinx, Inc., is distributed under license
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// from Xilinx, Inc., and may be used, copied and/or
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// disclosed only pursuant to the terms of a valid license
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// agreement with Xilinx, Inc. Xilinx hereby grants you
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// a license to use this text/file solely for design, simulation,
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// implementation and creation of design files limited
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// to Xilinx devices or technologies. Use with non-Xilinx
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// devices or technologies is expressly prohibited and
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// immediately terminates your license unless covered by
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// a separate agreement.
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//
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// Xilinx is providing this design, code, or information
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// "as is" solely for use in developing programs and
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// solutions for Xilinx devices. By providing this design,
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// code, or information as one possible implementation of
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// this feature, application or standard, Xilinx is making no
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// representation that this implementation is free from any
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// claims of infringement. You are responsible for
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// obtaining any rights you may require for your implementation.
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// Xilinx expressly disclaims any warranty whatsoever with
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// respect to the adequacy of the implementation, including
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// but not limited to any warranties or representations that this
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// implementation is free from claims of infringement, implied
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// warranties of merchantability or fitness for a particular
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// purpose.
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//
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// Xilinx products are not intended for use in life support
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// appliances, devices, or systems. Use in such applications are
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// expressly prohibited.
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//
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// This copyright and support notice must be retained as part
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// of this text at all times. (c) Copyright 2004-2008 Xilinx, Inc.
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// All rights reserved.
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//
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//-----------------------------------------------------------------------------
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// Description: This level:
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//
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// * instantiates the TEMAC top level file (the TEMAC
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// wrapper with the clocking and physical interface
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// logic;
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//
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// * instantiates TX and RX reference design FIFO's with
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// a local link interface.
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//
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// Please refer to the Datasheet, Getting Started Guide, and
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// the Virtex-5 Embedded Tri-Mode Ethernet MAC User Gude for
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// further information.
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//-----------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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//-----------------------------------------------------------------------------
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// The module declaration for the MAC with FIFO design.
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//-----------------------------------------------------------------------------
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module v5_emac_v1_6_locallink
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(
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// EMAC0 Clocking
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// 125MHz clock output from transceiver
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CLK125_OUT,
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// 125MHz clock input from BUFG
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CLK125,
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// Tri-speed clock output from EMAC0
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CLIENT_CLK_OUT_0,
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// EMAC0 Tri-speed clock input from BUFG
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CLIENT_CLK_0,
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// Local link Receiver Interface - EMAC0
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RX_LL_CLOCK_0,
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RX_LL_RESET_0,
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RX_LL_DATA_0,
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RX_LL_SOF_N_0,
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RX_LL_EOF_N_0,
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RX_LL_SRC_RDY_N_0,
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RX_LL_DST_RDY_N_0,
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RX_LL_FIFO_STATUS_0,
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// Local link Transmitter Interface - EMAC0
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TX_LL_CLOCK_0,
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TX_LL_RESET_0,
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TX_LL_DATA_0,
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TX_LL_SOF_N_0,
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TX_LL_EOF_N_0,
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TX_LL_SRC_RDY_N_0,
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TX_LL_DST_RDY_N_0,
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// Client Receiver Interface - EMAC0
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EMAC0CLIENTRXDVLD,
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EMAC0CLIENTRXFRAMEDROP,
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EMAC0CLIENTRXSTATS,
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EMAC0CLIENTRXSTATSVLD,
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EMAC0CLIENTRXSTATSBYTEVLD,
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// Client Transmitter Interface - EMAC0
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CLIENTEMAC0TXIFGDELAY,
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EMAC0CLIENTTXSTATS,
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EMAC0CLIENTTXSTATSVLD,
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EMAC0CLIENTTXSTATSBYTEVLD,
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// MAC Control Interface - EMAC0
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CLIENTEMAC0PAUSEREQ,
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CLIENTEMAC0PAUSEVAL,
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//EMAC-MGT link status
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EMAC0CLIENTSYNCACQSTATUS,
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EMAC0ANINTERRUPT,
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// SGMII Interface - EMAC0
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TXP_0,
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TXN_0,
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RXP_0,
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RXN_0,
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PHYAD_0,
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RESETDONE_0,
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// unused transceiver
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TXN_1_UNUSED,
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TXP_1_UNUSED,
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RXN_1_UNUSED,
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RXP_1_UNUSED,
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// SGMII MGT Clock buffer inputs
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CLK_DS,
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GTRESET,
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// Asynchronous Reset
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RESET
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);
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//-----------------------------------------------------------------------------
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// Port Declarations
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//-----------------------------------------------------------------------------
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// EMAC0 Clocking
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// 125MHz clock output from transceiver
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output CLK125_OUT;
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// 125MHz clock input from BUFG
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input CLK125;
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// Tri-speed clock output from EMAC0
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output CLIENT_CLK_OUT_0;
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// EMAC0 Tri-speed clock input from BUFG
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input CLIENT_CLK_0;
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// Local link Receiver Interface - EMAC0
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input RX_LL_CLOCK_0;
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input RX_LL_RESET_0;
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output [7:0] RX_LL_DATA_0;
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output RX_LL_SOF_N_0;
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output RX_LL_EOF_N_0;
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output RX_LL_SRC_RDY_N_0;
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input RX_LL_DST_RDY_N_0;
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output [3:0] RX_LL_FIFO_STATUS_0;
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// Local link Transmitter Interface - EMAC0
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input TX_LL_CLOCK_0;
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input TX_LL_RESET_0;
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input [7:0] TX_LL_DATA_0;
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input TX_LL_SOF_N_0;
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input TX_LL_EOF_N_0;
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input TX_LL_SRC_RDY_N_0;
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output TX_LL_DST_RDY_N_0;
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// Client Receiver Interface - EMAC0
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output EMAC0CLIENTRXDVLD;
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output EMAC0CLIENTRXFRAMEDROP;
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output [6:0] EMAC0CLIENTRXSTATS;
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output EMAC0CLIENTRXSTATSVLD;
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output EMAC0CLIENTRXSTATSBYTEVLD;
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// Client Transmitter Interface - EMAC0
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input [7:0] CLIENTEMAC0TXIFGDELAY;
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output EMAC0CLIENTTXSTATS;
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output EMAC0CLIENTTXSTATSVLD;
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output EMAC0CLIENTTXSTATSBYTEVLD;
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// MAC Control Interface - EMAC0
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input CLIENTEMAC0PAUSEREQ;
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input [15:0] CLIENTEMAC0PAUSEVAL;
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//EMAC-MGT link status
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output EMAC0CLIENTSYNCACQSTATUS;
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output EMAC0ANINTERRUPT;
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// SGMII Interface - EMAC0
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output TXP_0;
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output TXN_0;
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input RXP_0;
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input RXN_0;
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input [4:0] PHYAD_0;
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output RESETDONE_0;
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// unused transceiver
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output TXN_1_UNUSED;
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output TXP_1_UNUSED;
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input RXN_1_UNUSED;
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input RXP_1_UNUSED;
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// SGMII MGT Clock buffer inputs
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input CLK_DS;
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input GTRESET;
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// Asynchronous Reset
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input RESET;
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//-----------------------------------------------------------------------------
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// Wire and Reg Declarations
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//-----------------------------------------------------------------------------
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// Global asynchronous reset
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wire reset_i;
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// Client interface clocking signals - EMAC0
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wire tx_clk_0_i;
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wire rx_clk_0_i;
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// Internal client interface connections - EMAC0
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// Transmitter interface
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wire [7:0] tx_data_0_i;
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wire tx_data_valid_0_i;
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wire tx_underrun_0_i;
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wire tx_ack_0_i;
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wire tx_collision_0_i;
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wire tx_retransmit_0_i;
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// Receiver interface
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wire [7:0] rx_data_0_i;
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wire rx_data_valid_0_i;
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wire rx_good_frame_0_i;
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wire rx_bad_frame_0_i;
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// Registers for the EMAC receiver output
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reg [7:0] rx_data_0_r;
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reg rx_data_valid_0_r;
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reg rx_good_frame_0_r;
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reg rx_bad_frame_0_r;
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// Reset signals from the transceiver
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wire resetdone_0_i;
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// create a synchronous reset in the transmitter clock domain
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reg [5:0] tx_pre_reset_0_i;
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reg tx_reset_0_i;
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// create a synchronous reset in the receiver clock domain
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reg [5:0] rx_pre_reset_0_i;
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reg rx_reset_0_i;
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// synthesis attribute ASYNC_REG of rx_pre_reset_0_i is "TRUE";
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// synthesis attribute ASYNC_REG of tx_pre_reset_0_i is "TRUE";
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//-----------------------------------------------------------------------------
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// Main Body of Code
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//-----------------------------------------------------------------------------
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// Asynchronous reset input
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assign reset_i = RESET;
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//------------------------------------------------------------------------
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// Instantiate the EMAC Wrapper (v5_emac_v1_6_block.v)
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//------------------------------------------------------------------------
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v5_emac_v1_6_block v5_emac_block_inst
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(
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// EMAC0 Clocking
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// 125MHz clock output from transceiver
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.CLK125_OUT (CLK125_OUT),
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// 125MHz clock input from BUFG
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.CLK125 (CLK125),
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// Tri-speed clock output from EMAC0
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.CLIENT_CLK_OUT_0 (CLIENT_CLK_OUT_0),
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// EMAC0 Tri-speed clock input from BUFG
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.CLIENT_CLK_0 (CLIENT_CLK_0),
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// Client Receiver Interface - EMAC0
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.EMAC0CLIENTRXD (rx_data_0_i),
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.EMAC0CLIENTRXDVLD (rx_data_valid_0_i),
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.EMAC0CLIENTRXGOODFRAME (rx_good_frame_0_i),
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.EMAC0CLIENTRXBADFRAME (rx_bad_frame_0_i),
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.EMAC0CLIENTRXFRAMEDROP (EMAC0CLIENTRXFRAMEDROP),
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.EMAC0CLIENTRXSTATS (EMAC0CLIENTRXSTATS),
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.EMAC0CLIENTRXSTATSVLD (EMAC0CLIENTRXSTATSVLD),
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.EMAC0CLIENTRXSTATSBYTEVLD (EMAC0CLIENTRXSTATSBYTEVLD),
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// Client Transmitter Interface - EMAC0
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.CLIENTEMAC0TXD (tx_data_0_i),
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.CLIENTEMAC0TXDVLD (tx_data_valid_0_i),
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.EMAC0CLIENTTXACK (tx_ack_0_i),
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.CLIENTEMAC0TXFIRSTBYTE (1'b0),
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.CLIENTEMAC0TXUNDERRUN (tx_underrun_0_i),
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.EMAC0CLIENTTXCOLLISION (tx_collision_0_i),
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.EMAC0CLIENTTXRETRANSMIT (tx_retransmit_0_i),
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.CLIENTEMAC0TXIFGDELAY (CLIENTEMAC0TXIFGDELAY),
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.EMAC0CLIENTTXSTATS (EMAC0CLIENTTXSTATS),
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.EMAC0CLIENTTXSTATSVLD (EMAC0CLIENTTXSTATSVLD),
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.EMAC0CLIENTTXSTATSBYTEVLD (EMAC0CLIENTTXSTATSBYTEVLD),
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// MAC Control Interface - EMAC0
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.CLIENTEMAC0PAUSEREQ (CLIENTEMAC0PAUSEREQ),
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.CLIENTEMAC0PAUSEVAL (CLIENTEMAC0PAUSEVAL),
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//EMAC-MGT link status
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.EMAC0CLIENTSYNCACQSTATUS (EMAC0CLIENTSYNCACQSTATUS),
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.EMAC0ANINTERRUPT (EMAC0ANINTERRUPT),
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// SGMII Interface - EMAC0
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.TXP_0 (TXP_0),
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.TXN_0 (TXN_0),
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.RXP_0 (RXP_0),
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.RXN_0 (RXN_0),
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.PHYAD_0 (PHYAD_0),
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.RESETDONE_0 (resetdone_0_i),
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// unused transceiver
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.TXN_1_UNUSED (TXN_1_UNUSED),
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.TXP_1_UNUSED (TXP_1_UNUSED),
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.RXN_1_UNUSED (RXN_1_UNUSED),
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.RXP_1_UNUSED (RXP_1_UNUSED),
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// SGMII MGT Clock buffer inputs
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.CLK_DS (CLK_DS),
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.GTRESET (GTRESET),
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// Asynchronous Reset Input
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.RESET (reset_i));
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//-------------------------------------------------------------------
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// Instantiate the client side FIFO
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//-------------------------------------------------------------------
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eth_fifo_8 client_side_FIFO_emac0 (
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// EMAC transmitter client interface
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.tx_clk(tx_clk_0_i),
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.tx_reset(tx_reset_0_i),
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.tx_enable(1'b1),
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.tx_data(tx_data_0_i),
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.tx_data_valid(tx_data_valid_0_i),
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347 |
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.tx_ack(tx_ack_0_i),
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348 |
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.tx_underrun(tx_underrun_0_i),
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349 |
|
|
.tx_collision(tx_collision_0_i),
|
350 |
|
|
.tx_retransmit(tx_retransmit_0_i),
|
351 |
|
|
|
352 |
|
|
// Transmitter local link interface
|
353 |
|
|
.tx_ll_clock(TX_LL_CLOCK_0),
|
354 |
|
|
.tx_ll_reset(TX_LL_RESET_0),
|
355 |
|
|
.tx_ll_data_in(TX_LL_DATA_0),
|
356 |
|
|
.tx_ll_sof_in_n(TX_LL_SOF_N_0),
|
357 |
|
|
.tx_ll_eof_in_n(TX_LL_EOF_N_0),
|
358 |
|
|
.tx_ll_src_rdy_in_n(TX_LL_SRC_RDY_N_0),
|
359 |
|
|
.tx_ll_dst_rdy_out_n(TX_LL_DST_RDY_N_0),
|
360 |
|
|
.tx_fifo_status(),
|
361 |
|
|
.tx_overflow(),
|
362 |
|
|
|
363 |
|
|
// EMAC receiver client interface
|
364 |
|
|
.rx_clk(rx_clk_0_i),
|
365 |
|
|
.rx_reset(rx_reset_0_i),
|
366 |
|
|
.rx_enable(1'b1),
|
367 |
|
|
.rx_data(rx_data_0_r),
|
368 |
|
|
.rx_data_valid(rx_data_valid_0_r),
|
369 |
|
|
.rx_good_frame(rx_good_frame_0_r),
|
370 |
|
|
.rx_bad_frame(rx_bad_frame_0_r),
|
371 |
|
|
.rx_overflow(),
|
372 |
|
|
|
373 |
|
|
// Receiver local link interface
|
374 |
|
|
.rx_ll_clock(RX_LL_CLOCK_0),
|
375 |
|
|
.rx_ll_reset(RX_LL_RESET_0),
|
376 |
|
|
.rx_ll_data_out(RX_LL_DATA_0),
|
377 |
|
|
.rx_ll_sof_out_n(RX_LL_SOF_N_0),
|
378 |
|
|
.rx_ll_eof_out_n(RX_LL_EOF_N_0),
|
379 |
|
|
.rx_ll_src_rdy_out_n(RX_LL_SRC_RDY_N_0),
|
380 |
|
|
.rx_ll_dst_rdy_in_n(RX_LL_DST_RDY_N_0),
|
381 |
|
|
.rx_fifo_status(RX_LL_FIFO_STATUS_0));
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
//-------------------------------------------------------------------
|
385 |
|
|
// Create synchronous reset signals for use in the FIFO.
|
386 |
|
|
// A synchronous reset signal is created in each
|
387 |
|
|
// clock domain.
|
388 |
|
|
//-------------------------------------------------------------------
|
389 |
|
|
|
390 |
|
|
// Create synchronous reset in the transmitter clock domain.
|
391 |
|
|
always @(posedge tx_clk_0_i, posedge reset_i)
|
392 |
|
|
begin
|
393 |
|
|
if (reset_i === 1'b1)
|
394 |
|
|
begin
|
395 |
|
|
tx_pre_reset_0_i <= 6'h3F;
|
396 |
|
|
tx_reset_0_i <= 1'b1;
|
397 |
|
|
end
|
398 |
|
|
else
|
399 |
|
|
begin
|
400 |
|
|
if (resetdone_0_i == 1'b1)
|
401 |
|
|
begin
|
402 |
|
|
tx_pre_reset_0_i[0] <= 1'b0;
|
403 |
|
|
tx_pre_reset_0_i[5:1] <= tx_pre_reset_0_i[4:0];
|
404 |
|
|
tx_reset_0_i <= tx_pre_reset_0_i[5];
|
405 |
|
|
end
|
406 |
|
|
end
|
407 |
|
|
end
|
408 |
|
|
|
409 |
|
|
always @(posedge rx_clk_0_i, posedge reset_i)
|
410 |
|
|
begin
|
411 |
|
|
if (reset_i === 1'b1)
|
412 |
|
|
begin
|
413 |
|
|
rx_pre_reset_0_i <= 6'h3F;
|
414 |
|
|
rx_reset_0_i <= 1'b1;
|
415 |
|
|
end
|
416 |
|
|
else
|
417 |
|
|
begin
|
418 |
|
|
if (resetdone_0_i == 1'b1)
|
419 |
|
|
begin
|
420 |
|
|
rx_pre_reset_0_i[0] <= 1'b0;
|
421 |
|
|
rx_pre_reset_0_i[5:1] <= rx_pre_reset_0_i[4:0];
|
422 |
|
|
rx_reset_0_i <= rx_pre_reset_0_i[5];
|
423 |
|
|
end
|
424 |
|
|
end
|
425 |
|
|
end
|
426 |
|
|
|
427 |
|
|
|
428 |
|
|
//--------------------------------------------------------------------
|
429 |
|
|
// Register the receiver outputs from EMAC0 before routing
|
430 |
|
|
// to the FIFO
|
431 |
|
|
//--------------------------------------------------------------------
|
432 |
|
|
always @(posedge rx_clk_0_i, posedge reset_i)
|
433 |
|
|
begin
|
434 |
|
|
if (reset_i == 1'b1)
|
435 |
|
|
begin
|
436 |
|
|
rx_data_valid_0_r <= 1'b0;
|
437 |
|
|
rx_data_0_r <= 8'h00;
|
438 |
|
|
rx_good_frame_0_r <= 1'b0;
|
439 |
|
|
rx_bad_frame_0_r <= 1'b0;
|
440 |
|
|
end
|
441 |
|
|
else
|
442 |
|
|
begin
|
443 |
|
|
if (resetdone_0_i == 1'b1)
|
444 |
|
|
begin
|
445 |
|
|
rx_data_0_r <= rx_data_0_i;
|
446 |
|
|
rx_data_valid_0_r <= rx_data_valid_0_i;
|
447 |
|
|
rx_good_frame_0_r <= rx_good_frame_0_i;
|
448 |
|
|
rx_bad_frame_0_r <= rx_bad_frame_0_i;
|
449 |
|
|
end
|
450 |
|
|
end
|
451 |
|
|
end
|
452 |
|
|
|
453 |
|
|
assign EMAC0CLIENTRXDVLD = rx_data_valid_0_i;
|
454 |
|
|
|
455 |
|
|
// EMAC0 Clocking
|
456 |
|
|
assign tx_clk_0_i = CLIENT_CLK_0;
|
457 |
|
|
assign rx_clk_0_i = CLIENT_CLK_0;
|
458 |
|
|
|
459 |
|
|
assign RESETDONE_0 = resetdone_0_i;
|
460 |
|
|
|
461 |
|
|
endmodule
|