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CONFIG PART = 5vlx110tff1136-1;

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# BLOCK Level constraints

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# EMAC0 Clocking

# 125MHz clock input from BUFG

NET "enet_inst?CLK125" TNM_NET          = "clk_gtp";

TIMEGRP  "v5_emac_v1_6_gtp_clk"            = "clk_gtp";

TIMESPEC "TS_v5_emac_v1_6_gtp_clk"         = PERIOD "v5_emac_v1_6_gtp_clk" 7700 ps HIGH 50 %;

# EMAC0 Tri-speed clock input from BUFG

NET "enet_inst?CLIENT_CLK_0" TNM_NET    = "clk_client0";

TIMEGRP  "v5_emac_v1_6_gtp_clk_client0"    = "clk_client0";

TIMESPEC "TS_v5_emac_v1_6_gtp_clk_client0" = PERIOD "v5_emac_v1_6_gtp_clk_client0" 7700 ps HIGH 50 %;

# LocalLink clock groups

NET "clk_local" TNM_NET         = "clk_ll";

TIMEGRP "patlpp_sysclk"                 = "clk_ll";

TIMESPEC "TS_patlpp_sysclk"     = PERIOD "patlpp_sysclk" 13ns HIGH 50%;

#-----------------------------------------------------------

# EMAC0 Fabric Rx Elastic Buffer Timing Constraints:       -

#-----------------------------------------------------------

NET "*GTP_DUAL_1000X_inst?RXRECCLK_0_BUFR" TNM_NET = "clk_rec_clk0";

TIMEGRP  "v5_emac_v1_6_client_rec_clk0"                        = "clk_rec_clk0";

TIMESPEC "TS_v5_emac_v1_6_rec_clk0"                            = PERIOD "v5_emac_v1_6_client_rec_clk0" 7700 ps HIGH 50 %;

# Control Gray Code delay and skew

INST "*GTP_DUAL_1000X_inst?rx_elastic_buffer_inst_0?rd_addr_gray_?" TNM = "rx_elastic_rd_to_wr_0";

TIMESPEC "TS_rx_elastic_rd_to_wr_0" = FROM "rx_elastic_rd_to_wr_0" TO "clk_rec_clk0" 7500 ps DATAPATHONLY;

INST "*GTP_DUAL_1000X_inst?rx_elastic_buffer_inst_0?wr_addr_gray_?" TNM = "elastic_metastable_0";

TIMESPEC "ts_elastic_meta_protect_0" = FROM "elastic_metastable_0" 5 ns DATAPATHONLY;

# Reduce clock period to allow 3 ns for metastability settling time

INST "*GTP_DUAL_1000X_inst?rx_elastic_buffer_inst_0?rd_wr_addr_gray*" TNM = "rx_graycode_0";

INST "*GTP_DUAL_1000X_inst?rx_elastic_buffer_inst_0?rd_occupancy*"    TNM = "rx_binary_0";

TIMESPEC "ts_rx_buf_meta_protect_0" = FROM "rx_graycode_0" TO "rx_binary_0" 5 ns;

##################################

# LocalLink Level constraints

##################################

# EMAC0 LocalLink client FIFO constraints.

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_tran_frame_tog"    TNM = "tx_fifo_rd_to_wr_0";

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_retran_frame_tog"  TNM = "tx_fifo_rd_to_wr_0";

#INST "*client_side_FIFO_emac0?tx_fifo_i?rd_col_window_pipe_1" TNM = "tx_fifo_rd_to_wr_0";

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_addr_txfer*"       TNM = "tx_fifo_rd_to_wr_0";

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_txfer_tog"         TNM = "tx_fifo_rd_to_wr_0";

INST "*client_side_FIFO_emac0?tx_fifo_i?wr_frame_in_fifo"     TNM = "tx_fifo_wr_to_rd_0";

TIMESPEC "TS_tx_fifo_rd_to_wr_0" = FROM "tx_fifo_rd_to_wr_0" TO "v5_emac_v1_6_gtp_clk_client0" 8000 ps DATAPATHONLY;

TIMESPEC "TS_tx_fifo_wr_to_rd_0" = FROM "tx_fifo_wr_to_rd_0" TO "v5_emac_v1_6_gtp_clk_client0" 8000 ps DATAPATHONLY;

# Reduce clock period to allow 3 ns for metastability settling time

INST "*client_side_FIFO_emac0?tx_fifo_i?wr_tran_frame_tog"    TNM = "tx_metastable_0";

INST "*client_side_FIFO_emac0?tx_fifo_i?wr_rd_addr*"          TNM = "tx_metastable_0";

INST "*client_side_FIFO_emac0?tx_fifo_i?wr_txfer_tog"         TNM = "tx_metastable_0";

INST "*client_side_FIFO_emac0?tx_fifo_i?frame_in_fifo"        TNM = "tx_metastable_0";

INST "*client_side_FIFO_emac0?tx_fifo_i?wr_retran_frame_tog*" TNM = "tx_metastable_0";

#INST "*client_side_FIFO_emac0?tx_fifo_i?wr_col_window_pipe_0" TNM = "tx_metastable_0";

TIMESPEC "ts_tx_meta_protect_0" = FROM "tx_metastable_0" 5 ns DATAPATHONLY;

INST "*client_side_FIFO_emac0?tx_fifo_i?rd_addr_txfer*"       TNM = "tx_addr_rd_0";

INST "*client_side_FIFO_emac0?tx_fifo_i?wr_rd_addr*"          TNM = "tx_addr_wr_0";

TIMESPEC "TS_tx_fifo_addr_0" = FROM "tx_addr_rd_0" TO "tx_addr_wr_0" 10ns;

## RX Client FIFO

# Group the clock crossing signals into timing groups

INST "*client_side_FIFO_emac0?rx_fifo_i?wr_store_frame_tog"   TNM = "rx_fifo_wr_to_rd_0";

INST "*client_side_FIFO_emac0?rx_fifo_i?rd_addr_gray*"        TNM = "rx_fifo_rd_to_wr_0";

TIMESPEC "TS_rx_fifo_wr_to_rd_0" = FROM "rx_fifo_wr_to_rd_0" TO "v5_emac_v1_6_gtp_clk_client0" 8000 ps DATAPATHONLY;

TIMESPEC "TS_rx_fifo_rd_to_wr_0" = FROM "rx_fifo_rd_to_wr_0" TO "v5_emac_v1_6_gtp_clk_client0" 8000 ps DATAPATHONLY;

# Reduce clock period to allow for metastability settling time

INST "*client_side_FIFO_emac0?rx_fifo_i?wr_rd_addr_gray_sync*" TNM = "rx_metastable_0";

INST "*client_side_FIFO_emac0?rx_fifo_i?rd_store_frame_tog"    TNM = "rx_metastable_0";

TIMESPEC "ts_rx_meta_protect_0" = FROM "rx_metastable_0" 5 ns;

# Area constaint to place example design near embedded TEMAC. Constraint is

# optional and not necessary for a successful implementation of the design.

#INST v5_emac_ll/* AREA_GROUP = AG_v5_emac ;

#AREA_GROUP "AG_v5_emac" RANGE = CLOCKREGION_X1Y2,CLOCKREGION_X1Y3 ;

##################################

# EXAMPLE DESIGN Level constraints

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# Place the transceiver components. Please alter to your chosen transceiver.

INST "*GTP_DUAL_1000X_inst?GTP_1000X?tile0_rocketio_wrapper_i?gtp_dual_i" LOC = "GTP_DUAL_X0Y4";

#INST "enet_inst?MGTCLK_N" LOC = "P3";

#INST "enet_inst?MGTCLK_P" LOC = "P4";

INST "MGTCLK_N" LOC = "P3";

INST "MGTCLK_P" LOC = "P4";

#Added per tutorial

NET "GTP_READY" LOC = AF23; #LED W

NET "PHY_RESET_0" LOC = J14; #ML505 PHY Reset

NET "RESET" LOC = AJ6; # Push Button Center

NET "RESET_CPU" LOC = E9; # CPU Reset Button

#LED Status

NET "LEDS<0>" LOC = H18;

NET "LEDS<1>" LOC = L18;

NET "LEDS<2>" LOC = G15;

NET "LEDS<3>" LOC = AD26;

NET "LEDS<4>" LOC = G16;

NET "LEDS<5>" LOC = AD25;

NET "LEDS<6>" LOC = AD24;

NET "LEDS<7>" LOC = AE24;

#DIP Switches

NET "DIP<0>" LOC = U25;

NET "DIP<1>" LOC = AG27;

NET "DIP<2>" LOC = AF25;

NET "DIP<3>" LOC = AF26;

NET "DIP<4>" LOC = AE27;

NET "DIP<5>" LOC = AE26;

NET "DIP<6>" LOC = AC25;

NET "DIP<7>" LOC = AC24;