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[/] [fpga-cf/] [trunk/] [hdl/] [port_blank/] [port_blank.v] - Blame information for rev 8

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// 32 bit Port Register
 
`timescale 1ns/100ps
 
module port_blank(
        input                                   clk,
        input                                   rst,
        input                                   wen,
        input                                   ren,
        input                                   in_sof,
        input                                   in_eof,
        input                                   in_src_rdy,
        output                          in_dst_rdy,
        input           [7:0]            in_data,
 
        output  reg             out_sof,
        output  reg             out_eof,
        input                                   out_dst_rdy,
        output                          out_src_rdy,
        output  reg [7:0]                out_data
);
 
endmodule

Line No.	Rev	Author	Line
1	2	peteralieb	`// 32 bit Port Register`
2
3			`timescale 1ns/100ps
4
5			`module port_blank(`
6			`input clk,`
7			`input rst,`
8			`input wen,`
9			`input ren,`
10			`input in_sof,`
11			`input in_eof,`
12			`input in_src_rdy,`
13			`output in_dst_rdy,`
14			`input [7:0] in_data,`
15
16			`output reg out_sof,`
17			`output reg out_eof,`
18			`input out_dst_rdy,`
19			`output out_src_rdy,`
20			`output reg [7:0] out_data`
21			`);`
22
23			`endmodule`

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[/] [fpga-cf/] [trunk/] [hdl/] [port_blank/] [port_blank.v] - Blame information for rev 8