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[/] [fpga-cf/] [trunk/] [hdl/] [port_blank/] [port_blank.v] - Blame information for rev 8

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1 2 peteralieb
// 32 bit Port Register
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`timescale 1ns/100ps
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module port_blank(
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        input                                   clk,
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        input                                   rst,
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        input                                   wen,
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        input                                   ren,
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        input                                   in_sof,
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        input                                   in_eof,
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        input                                   in_src_rdy,
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        output                          in_dst_rdy,
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        input           [7:0]            in_data,
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        output  reg             out_sof,
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        output  reg             out_eof,
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        input                                   out_dst_rdy,
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        output                          out_src_rdy,
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        output  reg [7:0]                out_data
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);
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endmodule

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