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[/] [fpga-cf/] [trunk/] [hdl/] [port_icap/] [port_icap_buf.v] - Blame information for rev 9

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1 2 peteralieb 
module port_icap_buf (
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// ICAP Module for PATLPP port interface
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4 
        // Inputs:
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        clk,
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        rst,
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        en_wr,                  // Write Module Enable
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        en_rd,                  // Read Module Enable
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        in_data,                        // Input Data
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        in_sof,                 // Input Start of Frame
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        in_eof,                 // Input End of Frame
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        in_src_rdy,             // Input Source Ready
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        out_dst_rdy,    // Output Destination Ready
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        // Outputs:
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        out_data,               // Output Data
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        out_sof,                        // Output Start of Frame
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        out_eof,                        // Output End of Frame
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        out_src_rdy,    // Output Source Ready
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        in_dst_rdy//,   // Input Destination Ready
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        //chipscope_data
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);
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// Port mode declarations:
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        // Inputs:
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input   clk;
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input   rst;
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input   en_wr;
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input   en_rd;
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input   [7:0]    in_data;
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input   in_sof;
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input   in_eof;
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input   in_src_rdy;
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input   out_dst_rdy;
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        // Outputs:
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output  [7:0]    out_data;
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output  out_sof;
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output  out_eof;
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output  out_src_rdy;
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output  in_dst_rdy;
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//output        [19:0] chipscope_data;
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// Signals --------------------------------------------------------------------------------
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//ICAP
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wire                            icap_en_n;              // ICAP enable
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wire                            icap_wr_n;              // ICAP write (0: write, 1: read)
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wire    [7:0]            icap_din;               // ICAP Data In
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wire    [7:0]            icap_dout;              // ICAP Data Out
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wire                            icap_busy;              // ICAP Busy
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//Read FIFO
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wire                            rfifo_rd_en;    // Read enable
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wire                            rfifo_wr_en;    // Write enable
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wire    [7:0]            rfifo_din;              // Data In
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wire    [7:0]            rfifo_dout;             // Data Out
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wire                            rfifo_full;             // FIFO Full
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wire                            rfifo_empty;    // FIFO Empty
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//Registers
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reg                             icap_en_r;              // ICAP Enable Register
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reg                             icap_wr_r;              // ICAP Write Register
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reg     [7:0]            count_low_r;    // Count low bits
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reg     [7:0]            count_high_r;   // Count high bits
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reg     [10:0]   counter;                        // Counter
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reg                             count_en;               // Counter Enable
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reg                             can_write;              // Can write to the icap
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//FSM
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parameter       [2:0]            IDLE = 3'b000;
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parameter       [2:0]            S_WRITE = 3'b001;
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parameter       [2:0]            WRITE = 3'b010;
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parameter       [2:0]            E_WRITE = 3'b011;
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parameter       [2:0]            I_READ = 3'b100;
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parameter       [2:0]            S_READ = 3'b101;
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parameter       [2:0]            READ = 3'b110;
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reg     [2:0]            state;                  // Current state
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reg     [2:0]            next_state;             // Next State
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// Instantiations -------------------------------------------------------------------------
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shiftr_bram the_fifo
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(
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        .clk(clk),
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        .rst(rst),
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        .en_in(rfifo_wr_en),
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        .en_out(rfifo_rd_en),
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        .empty(rfifo_empty),
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        .full(rfifo_full),
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        .data_in(rfifo_din),
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        .data_out(rfifo_dout)
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);
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assign rfifo_wr_en = ((state == READ) && ~icap_wr_r && ~icap_busy) ? 1'b1 : 1'b0;
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assign rfifo_rd_en = en_rd & out_dst_rdy;
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assign rfifo_din = icap_dout;
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/* V5 Primitive */
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 ICAP_VIRTEX5 #(
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        .ICAP_WIDTH("X8")
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) icap_inst (
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        .CLK(clk),
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        .CE(icap_en_n),
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        .WRITE(icap_wr_n),
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        .I({icap_din[0], icap_din[1], icap_din[2], icap_din[3], icap_din[4], icap_din[5], icap_din[6], icap_din[7]}),
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        .BUSY(icap_busy),
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        .O({icap_dout[0], icap_dout[1], icap_dout[2], icap_dout[3], icap_dout[4], icap_dout[5], icap_dout[6], icap_dout[7]})
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);
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/**/
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/* V4 Primitive
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ICAP_VIRTEX4 #(
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        .ICAP_WIDTH("X8")
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) icap_inst (
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        .CLK(clk),
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        .CE(icap_en_n),
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        .WRITE(icap_wr_n),
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        .I({icap_din[0], icap_din[1], icap_din[2], icap_din[3], icap_din[4], icap_din[5], icap_din[6], icap_din[7]}),
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        .BUSY(icap_busy),
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        .O({icap_dout[0], icap_dout[1], icap_dout[2], icap_dout[3], icap_dout[4], icap_dout[5], icap_dout[6], icap_dout[7]})
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);
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*/
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// Test V4 ICAP
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// icap_virtex4test #(
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        // .ICAP_DWIDTH(8)
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// ) v4testicap (
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        // .clk(clk),
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        // .Rst(rst),
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        // .ce(icap_en_n),
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        // .write(icap_wr_n),
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        // .i({icap_din[0], icap_din[1], icap_din[2], icap_din[3], icap_din[4], icap_din[5], icap_din[6], icap_din[7]}),
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        // .busy(icap_busy),
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        // .o({icap_dout[0], icap_dout[1], icap_dout[2], icap_dout[3], icap_dout[4], icap_dout[5], icap_dout[6], icap_dout[7]})
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// );
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assign icap_en_n = ~icap_en_r;
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assign icap_wr_n = ~icap_wr_r;
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assign icap_din = in_data;
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// Behavior -------------------------------------------------------------------------------
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// Next State
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always @(en_wr or in_src_rdy or en_rd or counter or in_eof or en_rd or state)
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begin
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        case (state)
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        IDLE: begin
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                if (en_wr & in_src_rdy)
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                        next_state <= S_WRITE;
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                else if (en_rd & in_src_rdy)
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                        next_state <= I_READ;
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                else
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                        next_state <= IDLE;
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        end
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        S_WRITE: begin
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                if (en_wr & in_src_rdy)
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                        next_state <= WRITE;
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                else
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                        next_state <= S_WRITE;
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        end
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        WRITE: begin
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                if (en_wr & in_src_rdy & in_eof)
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                        next_state <= E_WRITE;
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                else
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                        next_state <= WRITE;
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        end
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        E_WRITE: begin
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                next_state <= IDLE;
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        end
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        I_READ: begin
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                 if (en_rd & in_src_rdy)
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                        next_state <= S_READ;
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                else
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                        next_state <= I_READ;
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        end
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        S_READ: begin
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                next_state <= READ;
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        end
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        READ: begin
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                if (counter == 1)
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                        next_state <= IDLE;
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                else
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                        next_state <= READ;
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        end
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        default: begin
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                next_state <= IDLE;
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        end
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        endcase
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end
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always @(posedge clk)
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begin
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        state <= next_state;
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end
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// Registers
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always @(posedge clk)
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begin
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        if (state == IDLE && en_rd && in_src_rdy)
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        begin
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                count_high_r <= in_data;
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        end
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        if (state == I_READ && en_rd && in_src_rdy)
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        begin
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                count_low_r <= in_data;
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        end
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        if (state == S_READ)
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        begin
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                counter <= {count_high_r, count_low_r};
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        end
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        else if (count_en)
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        begin
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                counter <= counter - 1;
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        end
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end
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// Outputs
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always @(state or en_wr or in_src_rdy or icap_busy or en_rd)
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begin
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        case (state)
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        IDLE: begin
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                icap_en_r = 0;
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                icap_wr_r = 0;
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                count_en = 0;
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                can_write = en_rd;
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        end
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        S_WRITE: begin
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                icap_en_r = 0;
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                icap_wr_r = 1;
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                count_en = 0;
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                can_write = 0;
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        end
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        WRITE: begin
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                icap_en_r = en_wr & in_src_rdy;
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                icap_wr_r = 1;
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                count_en = 0;
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                can_write = 1;
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        end
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        E_WRITE: begin
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                icap_en_r = 0;
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                icap_wr_r = 1;
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                count_en = 0;
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                can_write = 0;
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        end
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        I_READ: begin
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                icap_en_r = 0;
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                icap_wr_r = 0;
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                count_en = 0;
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                can_write = 1;
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        end
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        S_READ: begin
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                icap_en_r = 1;
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                icap_wr_r = 0;
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                count_en = 0;
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                can_write = 0;
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        end
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        READ: begin
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                icap_en_r = 1;
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                icap_wr_r = 0;
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                count_en = ~icap_busy;
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                can_write = 0;
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        end
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        default: begin
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                icap_en_r = 0;
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                icap_wr_r = 0;
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                count_en = 0;
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                can_write = 0;
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        end
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        endcase
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end
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assign out_data = rfifo_dout;
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assign out_sof = 0;
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assign out_eof = 0;
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assign out_src_rdy = ~rfifo_empty;
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assign in_dst_rdy = can_write;
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endmodule

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