URL https://opencores.org/ocsvn/fpga-cf/fpga-cf/trunk

Subversion Repositories fpga-cf

[/] [fpga-cf/] [trunk/] [hdl/] [port_icap/] [sim.do] - Blame information for rev 2

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quit -sim
 
vlog C:/Xilinx/11.1/ISE/verilog/src/glbl.v
vcom ../ICAP_VIRTEX4test/proc_common_pkg.vhd
vcom ../ICAP_VIRTEX4test/family_support.vhd
vcom ../ICAP_VIRTEX4test/muxf_struct_f.vhd
vcom ../ICAP_VIRTEX4test/cntr_incr_decr_addn_f.vhd
vcom ../ICAP_VIRTEX4test/dynshreg_f.vhd
vcom ../ICAP_VIRTEX4test/srl_fifo_rbu_f.vhd
vcom ../ICAP_VIRTEX4test/srl_fifo_f.vhd
vcom ../ICAP_VIRTEX4test/ICAP_VIRTEX4test.vhd
vlog ../PATLPP/shiftr_bram/shiftr_bram.v
vlog ./port_icap_buf.v
vlog ./port_icap_tb.v
 
vsim -L unisims_ver -L unimacro_ver -voptargs=+acc port_icap_tb glbl
 
add wave -hex /port_icap_tb/*
add wave -hex /port_icap_tb/DUT/*
 
run 400ns
 

Line No.	Rev	Author	Line
1	2	peteralieb	`quit -sim`
2
3			`vlog C:/Xilinx/11.1/ISE/verilog/src/glbl.v`
4			`vcom ../ICAP_VIRTEX4test/proc_common_pkg.vhd`
5			`vcom ../ICAP_VIRTEX4test/family_support.vhd`
6			`vcom ../ICAP_VIRTEX4test/muxf_struct_f.vhd`
7			`vcom ../ICAP_VIRTEX4test/cntr_incr_decr_addn_f.vhd`
8			`vcom ../ICAP_VIRTEX4test/dynshreg_f.vhd`
9			`vcom ../ICAP_VIRTEX4test/srl_fifo_rbu_f.vhd`
10			`vcom ../ICAP_VIRTEX4test/srl_fifo_f.vhd`
11			`vcom ../ICAP_VIRTEX4test/ICAP_VIRTEX4test.vhd`
12			`vlog ../PATLPP/shiftr_bram/shiftr_bram.v`
13			`vlog ./port_icap_buf.v`
14			`vlog ./port_icap_tb.v`
15
16			`vsim -L unisims_ver -L unimacro_ver -voptargs=+acc port_icap_tb glbl`
17
18			`add wave -hex /port_icap_tb/*`
19			`add wave -hex /port_icap_tb/DUT/*`
20
21			`run 400ns`
22

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Subversion Repositories fpga-cf

[/] [fpga-cf/] [trunk/] [hdl/] [port_icap/] [sim.do] - Blame information for rev 2