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[/] [fpga-cf/] [trunk/] [hdl/] [sha1/] [port_sha1.v] - Blame information for rev 2

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1 2 peteralieb
// sha1 FCP Channel Interface
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`timescale 1ns/100ps
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module port_sha1(
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        input                                   clk,
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        input                                   rst,
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        input                                   wen,
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        input                                   ren,
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        input                                   in_sof,
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        input                                   in_eof,
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        input                                   in_src_rdy,
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        output                          in_dst_rdy,
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        input           [7:0]            in_data,
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        output                          out_sof,
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        output                          out_eof,
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        input                                   out_dst_rdy,
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        output                          out_src_rdy,
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        output  [7:0]            out_data
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);
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//------------------------------------------------------------------
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//---------------- sha1 Signals 
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//------------------------------------------------------------------
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wire    [31:0]   sha1_data_in;
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wire    [159:0]  sha1_cv_next;
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wire    [159:0]  sha1_cv;
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wire                            sha1_load_in;
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wire                            sha1_start;
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wire                            sha1_use_prev_cv;
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wire                            sha1_busy;
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wire                            sha1_out_valid;
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//------------------------------------------------------------------
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//---------------- Write FSM Signals
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//------------------------------------------------------------------
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reg                             in_sof_d;
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wire                            in_byte_en;
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reg                             in_byte_en_d;
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reg                             in_byte_en_dd;
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reg     [159:0]  in_data_d;
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reg                             in_eof_d;
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reg                             load_byte_en;
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reg                             load_word_en;
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reg                             start;
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reg                             use_prev_cv;
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reg                             rdy;
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reg [3:0]        wfsm_state;
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reg [3:0]        wnext_state;
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reg [3:0]        word_count;
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reg                     word_count_en;
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reg                     word_count_rst;
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wire                    wc_rst;
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reg     [23:0]   in_word_reg;
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`define WAIT                    4'd0
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`define LD_BYTE_0               4'd1
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`define LD_BYTE_1               4'd2
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`define LD_BYTE_2               4'd3
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`define LD_WORD         4'd4
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`define WAIT_BSY                4'd5
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`define WAIT_BSY_VLD    4'd6
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`define START                   4'd7
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//------------------------------------------------------------------
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//---------------- Read FSM Signals
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//------------------------------------------------------------------
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reg [4:0]        rcount;
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reg rcount_rst, rcount_dec, res_byte_en, rload;
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reg [1:0]        rfsm_state;
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reg [1:0]        rnext_state;
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reg     [159:0]  out_word_reg;
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`define WAIT_READ               2'd0
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`define RDY_READ                2'd1
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`define READING         2'd2
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//------------------------------------------------------------------
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//---------------- Read FSM
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//------------------------------------------------------------------
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assign out_byte_en = ren & out_dst_rdy;
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// Next State
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always @(rfsm_state or sha1_out_valid or rcount or out_byte_en)
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begin
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        case (rfsm_state)
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        `WAIT_READ: rnext_state = sha1_out_valid ? `RDY_READ : `WAIT_READ;
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        `RDY_READ: rnext_state = out_byte_en ? `READING : `RDY_READ;
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        `READING: rnext_state = (rcount == 0) ? `WAIT_READ : `READING;
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        default: rnext_state = `WAIT_READ;
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        endcase
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end
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always @(posedge clk or posedge rst)
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begin
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        if (rst) rfsm_state <= 0;
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        else rfsm_state <= rnext_state;
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end
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// Mealy Outputs
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always @(rfsm_state or sha1_out_valid or out_byte_en or rcount)
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begin
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        rcount_dec = 0;
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        rcount_rst = 0;
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        rload = 0;
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        case (rfsm_state)
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        `WAIT_READ: begin
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                if (sha1_out_valid)
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                begin
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                        rload = 1;
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                        rcount_rst = 1;
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                end
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        end
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        `RDY_READ: begin
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                if (out_byte_en) rcount_dec = 1;
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        end
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        `READING: begin
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                if (out_byte_en == 1) rcount_dec = 1;
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        end
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        endcase
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end
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// Moore Output
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always @(rfsm_state)
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begin
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        case (rfsm_state)
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        `WAIT_READ: res_byte_en = 0;
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        `RDY_READ: res_byte_en = 1;
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        `READING: res_byte_en = 1;
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        default: res_byte_en = 0;
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        endcase
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end
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144
//------------------------------------------------------------------
145
//---------------- Write FSM
146
//------------------------------------------------------------------
147
 
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assign in_byte_en = wen & in_src_rdy;
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// Next State
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always @(wfsm_state or in_byte_en or sha1_out_valid or in_sof or in_eof or word_count or sha1_busy or in_eof_d)
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begin
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        case (wfsm_state)
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        `WAIT: wnext_state = (in_byte_en & in_sof) ? `LD_BYTE_0 : `WAIT;
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        `LD_BYTE_0: wnext_state = (in_byte_en) ? `LD_BYTE_1 : `LD_BYTE_0;
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        `LD_BYTE_1: wnext_state = (in_byte_en) ? `LD_BYTE_2 : `LD_BYTE_1;
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        `LD_BYTE_2: wnext_state = (in_byte_en) ? `LD_WORD : `LD_BYTE_2;
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        `LD_WORD: wnext_state = (in_byte_en & ~in_eof & (word_count < 15)) ? `LD_BYTE_0 :
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                                                                        (in_byte_en & (word_count == 15)) ? `START : `LD_WORD;
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        `WAIT_BSY: wnext_state = (~sha1_busy) ? `LD_BYTE_0 : `WAIT_BSY;
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        `WAIT_BSY_VLD: wnext_state = (~sha1_busy & sha1_out_valid) ? `WAIT : `WAIT_BSY_VLD;
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        `START: wnext_state = (in_eof_d) ? `WAIT_BSY_VLD : `WAIT_BSY;
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        default: wnext_state = `WAIT;
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        endcase
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end
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always @(posedge clk or posedge rst)
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begin
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        if (rst) wfsm_state <= 0;
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        else wfsm_state <= wnext_state;
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172
        if (rst)
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        begin
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                in_sof_d <= 0;
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           in_eof_d <= 0;
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           in_byte_en_d <= 0;
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           in_data_d <= 0;
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        end
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        else
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        begin
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                in_sof_d <= in_sof;
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                in_eof_d <= in_eof;
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                in_byte_en_d <= in_byte_en;
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                in_data_d <= in_data;
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        end
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        if (rst) use_prev_cv <= 0;
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        else if (wfsm_state == `WAIT) use_prev_cv <= 0;
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        else if (wfsm_state == `WAIT_BSY) use_prev_cv <= 1;
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end
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assign wc_rst = rst | word_count_rst;
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always @(posedge clk or posedge wc_rst)
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begin
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        if (wc_rst) word_count <= 0;
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        else if (word_count_en) word_count <= word_count + 1;
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end
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// Moore Outputs
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always @(wfsm_state)
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begin
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        load_byte_en = 0;
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        load_word_en = 0;
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        start = 0;
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        word_count_en = 0;
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        word_count_rst = 0;
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        rdy = 0;
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        case (wfsm_state)
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        `WAIT: begin
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        end
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        `LD_BYTE_0: begin
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                load_byte_en = 1;
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                rdy = 1;
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        end
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        `LD_BYTE_1: begin
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                load_byte_en = 1;
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                rdy = 1;
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        end
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        `LD_BYTE_2: begin
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                load_byte_en = 1;
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                rdy = 1;
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        end
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        `LD_WORD: begin
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                load_word_en = 1;
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                word_count_en = in_byte_en;
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                rdy = 1;
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        end
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        `WAIT_BSY: begin
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        end
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        `WAIT_BSY_VLD: begin
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        end
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        `START: begin
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                start = 1;
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                word_count_rst = 1;
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        end
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        endcase
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end
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240
//------------------------------------------------------------------
241
//---------------- rcount Register
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//------------------------------------------------------------------
243
wire rst_or_rcount_rst;
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assign rst_or_rcount_rst = rst | rcount_rst;
245
 
246
always @(posedge clk or posedge rst_or_rcount_rst)
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begin
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        if (rst_or_rcount_rst) rcount <= 5'd20;
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        else if (rcount_dec) rcount <= rcount - 1;
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end
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252
//------------------------------------------------------------------
253
//---------------- In Word Register
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//------------------------------------------------------------------
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always @(posedge clk or posedge rst)
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begin
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        if (rst) in_word_reg <= 0;
259
        else if (load_byte_en & in_byte_en)
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        begin
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                in_word_reg[7:0]         <= in_data;
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                in_word_reg[15:8]               <= in_word_reg[7:0];
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                in_word_reg[23:16]      <= in_word_reg[15:8];
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        end
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end
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//------------------------------------------------------------------
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//---------------- Out Word Register
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//------------------------------------------------------------------
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271
always @(posedge clk or posedge rst)
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begin
273
        if (rst) out_word_reg <= 0;
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        else if (rload) out_word_reg <= sha1_cv_next;
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        else if (res_byte_en & out_byte_en)
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        begin
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                out_word_reg[7:0]                        <= 0;
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                out_word_reg[15:8]              <= out_word_reg[7:0];
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                out_word_reg[23:16]             <= out_word_reg[15:8];
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                out_word_reg[31:24]             <= out_word_reg[23:16];
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                out_word_reg[39:32]             <= out_word_reg[31:24];
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                out_word_reg[47:40]             <= out_word_reg[39:32];
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                out_word_reg[55:48]             <= out_word_reg[47:40];
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                out_word_reg[63:56]             <= out_word_reg[55:48];
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                out_word_reg[71:64]             <= out_word_reg[63:56];
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                out_word_reg[79:72]             <= out_word_reg[71:64];
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                out_word_reg[87:80]             <= out_word_reg[79:72];
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                out_word_reg[95:88]             <= out_word_reg[87:80];
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                out_word_reg[103:96]            <= out_word_reg[95:88];
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                out_word_reg[111:104]   <= out_word_reg[103:96];
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                out_word_reg[119:112]   <= out_word_reg[111:104];
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                out_word_reg[127:120]   <= out_word_reg[119:112];
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                out_word_reg[135:128]   <= out_word_reg[127:120];
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                out_word_reg[143:136]   <= out_word_reg[135:128];
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                out_word_reg[151:144]   <= out_word_reg[143:136];
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                out_word_reg[159:152]   <= out_word_reg[151:144];
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        end
298
end
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300
//------------------------------------------------------------------
301
//---------------- sha1 Instance
302
//------------------------------------------------------------------
303
 
304
assign sha1_start = start;
305
assign sha1_data_in = {in_word_reg, in_data};
306
assign sha1_load_in = load_word_en & in_byte_en;
307
assign sha1_use_prev_cv = use_prev_cv;
308
 
309
sha1_exec thesha1 (
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        .clk(clk),
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        .reset(rst),
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        .start(sha1_start),
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        .data_in(sha1_data_in),
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        .load_in(sha1_load_in),
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        .cv(160'h67452301EFCDAB8998BADCFE10325476C3D2E1F0),
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        .use_prev_cv(sha1_use_prev_cv),
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        .busy(sha1_busy),
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        .out_valid(sha1_out_valid),
319
        .cv_next(sha1_cv_next)
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);
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322
//------------------------------------------------------------------
323
//---------------- Output Logic
324
//------------------------------------------------------------------
325
 
326
assign in_dst_rdy = rdy;
327
assign out_data = out_word_reg[159:152];
328
assign out_sof = (rfsm_state == `RDY_READ) ? 1 : 0;
329
assign out_eof = (rfsm_state == `READING && rcount == 0) ? 1 : 0;
330
assign out_src_rdy = res_byte_en;
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332
endmodule

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