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[/] [fpga-cf/] [trunk/] [hdl/] [sha1/] [port_sha1_tb.v] - Blame information for rev 9

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1 2 peteralieb 
// Port MD5 Testbench
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`timescale 1ns / 100ps
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module port_sha1_tb;
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// Input stimulus:
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reg     clk;
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reg     rst;
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reg     en;
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reg     [7:0]    in_data;
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reg     in_sof;
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reg     in_eof;
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reg     in_src_rdy;
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reg     out_dst_rdy;
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// Output connections:
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wire    [7:0]    out_data;
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wire    out_sof;
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wire    out_eof;
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wire    out_src_rdy;
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wire    in_dst_rdy;
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//Instantiate the DUT (device under test):
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port_sha1 DUT (
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        // Inputs:
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        .clk ( clk ),
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        .rst ( rst ),
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        .wen ( en ),
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        .ren ( en ),
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        .in_data ( in_data ),   // Input
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        .in_sof ( in_sof ),     // Input
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        .in_eof ( in_eof ),     // Input
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        .in_src_rdy ( in_src_rdy ),     // Input
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        .out_dst_rdy ( out_dst_rdy ),   // Output
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        // Outputs:
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        .out_data ( out_data ), // Output
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        .out_sof ( out_sof ),   // Output
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        .out_eof ( out_eof ),   // Output
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        .out_src_rdy ( out_src_rdy ),   // Output
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        .in_dst_rdy ( in_dst_rdy )      // Input
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);
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        // Specify input stimulus:
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initial begin
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        // Initial values for input stimulus:
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        clk = 1;
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        rst = 1'b0;
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        en = 1'b0;
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        in_data = 8'b0;
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        in_sof = 1'b0;
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        in_eof = 1'b0;
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        in_src_rdy = 1'b1;
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        out_dst_rdy = 1'b0;
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        //
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        //--- INSERT YOUR INPUT STIMULUS DESCRIPTION HERE ---
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        //
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        @(posedge clk);
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        rst = 1;
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        @(posedge clk);
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        rst = 0;
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        @(posedge clk);
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        en = 0;
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        in_sof = 1;
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        in_src_rdy = 1;
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        in_data = "s";
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        #1 en = 1;
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        wait (in_dst_rdy);
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        @(posedge clk);
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        in_sof = 0;
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        in_data = "u";
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        @(posedge clk);
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        in_data = "b";
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        @(posedge clk);
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        in_data = "a";
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        @(posedge clk);
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        in_data = "r";
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        @(posedge clk);
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        in_data = "u";
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        @(posedge clk);
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        in_data = 8'h80;
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        @(posedge clk);
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        in_data = 8'h0;
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        in_src_rdy = 0;
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        en = 0;
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        @(posedge clk);
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        in_src_rdy = 1;
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        en = 1;
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        //in_data = 8'h80;
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        @(posedge clk);
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        //in_data = 8'h00;
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        //in_data = 8'h03;
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        @(posedge clk);
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        in_eof = 1;
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        in_data = 8'h30;
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        @(posedge clk);
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        in_eof = 0;
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        in_src_rdy = 0;
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        wait (out_src_rdy);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        @(posedge clk);
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        $stop;
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end
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        // Template for master clock. Uncomment and modify signal name as needed.
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        // Remember to set the initial value of 'Clock' in the 'initial' block above.
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always #5 clk = ~clk;
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always @(posedge clk)
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        out_dst_rdy = ~out_dst_rdy;
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endmodule

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