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[/] [fpga-cf/] [trunk/] [hdl/] [topv5_sha1.v] - Blame information for rev 2

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1 2 peteralieb
// Top Module
2
 
3
module top
4
(
5
   // SGMII Interface - EMAC0
6
   TXP_0,
7
   TXN_0,
8
   RXP_0,
9
   RXN_0,
10
 
11
   // SGMII MGT Clock buffer inputs 
12
   MGTCLK_N,
13
   MGTCLK_P,
14
 
15
   // reset for ethernet phy
16
   PHY_RESET_0,
17
 
18
   // GTP link status
19
   GTP_READY,
20
 
21
   // Asynchronous Reset
22
   RESET,
23
 
24
        // LED Status
25
        LEDS,
26
 
27
        // DIP Switch
28
        DIP,
29
 
30
        // CPU RESET
31
        RESET_CPU
32
);
33
 
34
//-----------------------------------------------------------------------------
35
// Port Declarations 
36
//-----------------------------------------------------------------------------
37
 
38
   // SGMII Interface - EMAC0
39
   output          TXP_0;
40
   output          TXN_0;
41
   input           RXP_0;
42
   input           RXN_0;
43
 
44
   // SGMII MGT Clock buffer inputs 
45
   input           MGTCLK_N;
46
   input           MGTCLK_P;
47
 
48
   // reset for ethernet phy
49
   output          PHY_RESET_0;
50
 
51
   // GTP link status
52
   output          GTP_READY;
53
 
54
   // Asynchronous Reset
55
   input           RESET;
56
 
57
        // LED Status
58
        output  [7:0]            LEDS;
59
 
60
        // DIP Switches
61
        input   [7:0]            DIP;
62
 
63
        // CPU RESET
64
        input                           RESET_CPU;
65
 
66
//-----------------------------------------------------------------------------
67
 
68
 
69
//-------------------------------------------------------------------------------------
70
//-------------------------------------------------------------------------------------
71
//                                                       User Signals
72
//-------------------------------------------------------------------------------------
73
//-------------------------------------------------------------------------------------
74
 
75
reg [7:0] DIP_r;
76
wire reset_cpu_p;
77
wire reset_cpu_i;
78
reg [7:0] LEDr;
79
 
80
 
81
//-----------------------------------------------------------------------------
82
// Ethernet Platform Instance
83
//-----------------------------------------------------------------------------
84
// This needs to be instantiated like this.  The first 10 signals get routed 
85
// through the top layer to pins.  The UCF (xupv5) has constraints for these ports.
86
//
87
// All the clock and input buffers are contained within the enetplatform module, 
88
// except for the RESET_CPU.  This is left to the user.  The rest of the ports 
89
// are routed to the channel interface.
90
//-----------------------------------------------------------------------------
91
 
92
wire in_src_rdy_usr;
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wire out_dst_rdy_usr;
94
wire [7:0] in_data_usr;
95
wire in_sof_usr;
96
wire in_eof_usr;
97
wire in_dst_rdy_usr;
98
wire out_src_rdy_usr;
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wire [7:0] out_data_usr;
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wire out_sof_usr;
101
wire out_eof_usr;
102
wire [3:0] outport_usr;
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wire [3:0] inport_usr;
104
wire clk_local;
105
 
106
 
107
enetplatform enet_inst
108
(
109
   .TXP_0(TXP_0),
110
   .TXN_0(TXN_0),
111
   .RXP_0(RXP_0),
112
   .RXN_0(RXN_0),
113
   .MGTCLK_N(MGTCLK_N),
114
   .MGTCLK_P(MGTCLK_P),
115
   .PHY_RESET_0(PHY_RESET_0),
116
   .GTP_READY(GTP_READY),
117
   .RESET(RESET),
118
        .RESET_CPU(reset_cpu_p),
119
        .in_src_rdy_usr(in_src_rdy_usr),
120
        .out_dst_rdy_usr(out_dst_rdy_usr),
121
        .in_data_usr(in_data_usr),
122
        .in_sof_usr(in_sof_usr),
123
        .in_eof_usr(in_eof_usr),
124
        .in_dst_rdy_usr(in_dst_rdy_usr),
125
        .out_src_rdy_usr(out_src_rdy_usr),
126
        .out_data_usr(out_data_usr),
127
        .out_sof_usr(out_sof_usr),
128
        .out_eof_usr(out_eof_usr),
129
        .outport_usr(outport_usr),
130
        .inport_usr(inport_usr),
131
        .clk_local(clk_local)
132
);
133
 
134
//-------------------------------------------------------------------------------------
135
//-------------------------------------------------------------------------------------
136
 
137
 
138
//-------------------------------------------------------------------------------------
139
//-------------------------------------------------------------------------------------
140
//                                                       ICAP Logic
141
//-------------------------------------------------------------------------------------
142
// The ICAP modules has special considerations that can be ignored when not used.
143
//-------------------------------------------------------------------------------------
144
 
145
wire icap_en_wr;
146
wire icap_en_rd;
147
wire icap_out_src_rdy;
148
wire icap_out_dst_rdy;
149
wire icap_in_src_rdy;
150
wire icap_in_dst_rdy;
151
wire icap_out_sof;
152
wire icap_out_eof;
153
wire icap_in_sof;
154
wire icap_in_eof;
155
wire [7:0] icap_dataout;
156
wire [7:0] icap_datain;
157
 
158
port_icap_buf the_picap
159
(
160
        .clk(clk_local),
161
        .rst(reset_cpu_p),
162
        .en_wr(icap_en_wr),
163
        .en_rd(icap_en_rd),
164
        .in_data(icap_datain),
165
        .in_sof(icap_in_sof),
166
        .in_eof(icap_in_eof),
167
        .in_src_rdy(icap_in_src_rdy),
168
        .out_dst_rdy(icap_out_dst_rdy),
169
        .out_data(icap_dataout),
170
        .out_sof(icap_out_sof),
171
        .out_eof(icap_out_eof),
172
        .out_src_rdy(icap_out_src_rdy),
173
        .in_dst_rdy(icap_in_dst_rdy)
174
);
175
 
176
assign icap_en_wr = ((outport_usr == 3 && out_src_rdy_usr == 1) || (inport_usr == 3 && in_dst_rdy_usr == 1)) ? 1 : 0;
177
assign icap_en_rd = ((outport_usr == 4 && out_src_rdy_usr == 1) || (inport_usr == 4 && in_dst_rdy_usr == 1)) ? 1 : 0;
178
//assign in_src_rdy_usr =       (inport_usr == 3 || inport_usr == 4) ? icap_out_src_rdy : 1;
179
//assign out_dst_rdy_usr = (outport_usr == 3 || outport_usr == 4) ? icap_in_dst_rdy : 1;
180
//assign in_sof_usr = (inport_usr == 3 || inport_usr == 4) ? icap_sofout : 1;
181
//assign in_eof_usr = (inport_usr == 3 || inport_usr == 4) ? icap_eofout : 1;
182
//assign in_data_usr = (inport_usr == 3 || inport_usr == 4) ? icap_dataout : DIP_r;
183
 
184
 
185
//-------------------------------------------------------------------------------------
186
//-------------------------------------------------------------------------------------
187
//                                                       Channel Routing
188
//-------------------------------------------------------------------------------------
189
// Create the set of interface wires for each channel.
190
//-------------------------------------------------------------------------------------
191
 
192
wire ch1_in_sof;
193
wire ch1_in_eof;
194
wire ch1_in_src_rdy;
195
wire ch1_in_dst_rdy;
196
wire [7:0] ch1_in_data;
197
wire ch1_out_sof;
198
wire ch1_out_eof;
199
wire ch1_out_src_rdy;
200
wire ch1_out_dst_rdy;
201
wire [7:0] ch1_out_data;
202
wire ch1_wen;
203
wire ch1_ren;
204
 
205
wire ch2_in_sof;
206
wire ch2_in_eof;
207
wire ch2_in_src_rdy;
208
wire ch2_in_dst_rdy;
209
wire [7:0] ch2_in_data;
210
wire ch2_out_sof;
211
wire ch2_out_eof;
212
wire ch2_out_src_rdy;
213
wire ch2_out_dst_rdy;
214
wire [7:0] ch2_out_data;
215
wire ch2_wen;
216
wire ch2_ren;
217
 
218
wire ch3_in_sof;
219
wire ch3_in_eof;
220
wire ch3_in_src_rdy;
221
wire ch3_in_dst_rdy;
222
wire [7:0] ch3_in_data;
223
wire ch3_out_sof;
224
wire ch3_out_eof;
225
wire ch3_out_src_rdy;
226
wire ch3_out_dst_rdy;
227
wire [7:0] ch3_out_data;
228
wire ch3_wen;
229
wire ch3_ren;
230
 
231
wire ch4_in_sof;
232
wire ch4_in_eof;
233
wire ch4_in_src_rdy;
234
wire ch4_in_dst_rdy;
235
wire [7:0] ch4_in_data;
236
wire ch4_out_sof;
237
wire ch4_out_eof;
238
wire ch4_out_src_rdy;
239
wire ch4_out_dst_rdy;
240
wire [7:0] ch4_out_data;
241
wire ch4_wen;
242
wire ch4_ren;
243
 
244
channelif4 channelif_inst
245
(
246
        .in_sof(out_sof_usr),
247
        .in_eof(out_eof_usr),
248
        .in_src_rdy(out_src_rdy_usr),
249
        .in_dst_rdy(out_dst_rdy_usr),
250
        .in_data(out_data_usr),
251
        .inport_addr(outport_usr),
252
        .out_sof(in_sof_usr),
253
        .out_eof(in_eof_usr),
254
        .out_src_rdy(in_src_rdy_usr),
255
        .out_dst_rdy(in_dst_rdy_usr),
256
        .out_data(in_data_usr),
257
        .outport_addr(inport_usr),
258
        .wenables(),
259
        .renables(),
260
 
261
        .ch1_in_sof(ch1_in_sof),
262
        .ch1_in_eof(ch1_in_eof),
263
        .ch1_in_src_rdy(ch1_in_src_rdy),
264
        .ch1_in_dst_rdy(ch1_in_dst_rdy),
265
        .ch1_in_data(ch1_in_data),
266
        .ch1_out_sof(ch1_out_sof),
267
        .ch1_out_eof(ch1_out_eof),
268
        .ch1_out_src_rdy(ch1_out_src_rdy),
269
        .ch1_out_dst_rdy(ch1_out_dst_rdy),
270
        .ch1_out_data(ch1_out_data),
271
        .ch1_wen(ch1_wen),
272
        .ch1_ren(ch1_ren),
273
 
274
        .ch2_in_sof(ch2_in_sof),
275
        .ch2_in_eof(ch2_in_eof),
276
        .ch2_in_src_rdy(ch2_in_src_rdy),
277
        .ch2_in_dst_rdy(ch2_in_dst_rdy),
278
        .ch2_in_data(ch2_in_data),
279
        .ch2_out_sof(ch2_out_sof),
280
        .ch2_out_eof(ch2_out_eof),
281
        .ch2_out_src_rdy(ch2_out_src_rdy),
282
        .ch2_out_dst_rdy(ch2_out_dst_rdy),
283
        .ch2_out_data(ch2_out_data),
284
        .ch2_wen(ch2_wen),
285
        .ch2_ren(ch2_ren),
286
 
287
        .ch3_in_sof(ch3_in_sof),
288
        .ch3_in_eof(ch3_in_eof),
289
        .ch3_in_src_rdy(ch3_in_src_rdy),
290
        .ch3_in_dst_rdy(ch3_in_dst_rdy),
291
        .ch3_in_data(ch3_in_data),
292
        .ch3_out_sof(ch3_out_sof),
293
        .ch3_out_eof(ch3_out_eof),
294
        .ch3_out_src_rdy(ch3_out_src_rdy),
295
        .ch3_out_dst_rdy(ch3_out_dst_rdy),
296
        .ch3_out_data(ch3_out_data),
297
        .ch3_wen(ch3_wen),
298
        .ch3_ren(ch3_ren),
299
 
300
        .ch4_in_sof(ch4_in_sof),
301
        .ch4_in_eof(ch4_in_eof),
302
        .ch4_in_src_rdy(ch4_in_src_rdy),
303
        .ch4_in_dst_rdy(ch4_in_dst_rdy),
304
        .ch4_in_data(ch4_in_data),
305
        .ch4_out_sof(ch4_out_sof),
306
        .ch4_out_eof(ch4_out_eof),
307
        .ch4_out_src_rdy(ch4_out_src_rdy),
308
        .ch4_out_dst_rdy(ch4_out_dst_rdy),
309
        .ch4_out_data(ch4_out_data),
310
        .ch4_wen(ch4_wen),
311
        .ch4_ren(ch4_ren)
312
);
313
 
314
 
315
//-------------------------------------------------------------------------------------
316
//-------------------------------------------------------------------------------------
317
//                                                       User Logic
318
//-------------------------------------------------------------------------------------
319
// Place logic or port modules here.  You can see how the md5 modules is connected to 
320
// the channel 2 data and control lines.  
321
//-------------------------------------------------------------------------------------
322
 
323
wire [7:0] LEDnext;
324
 
325
IBUF cpu_reset_ibuf (.I(RESET_CPU), .O(reset_cpu_i));
326
 
327
assign reset_cpu_p = ~reset_cpu_i;
328
assign LEDS = LEDr;
329
 
330
always @(posedge clk_local)
331
begin
332
        DIP_r <= DIP;
333
end
334
 
335
always @(posedge clk_local)
336
begin
337
        if (reset_cpu_p)
338
                LEDr <= 0;
339
        else if (ch1_wen & ch1_out_src_rdy)
340
                LEDr <= LEDnext;
341
end
342
 
343
// MD5 module
344
port_sha1 sha1 (
345
        // Inputs:
346
        .clk ( clk_local ),
347
        .rst ( reset_cpu_p ),
348
        .wen ( ch2_wen ),
349
        .ren ( ch2_ren ),
350
        .in_data ( ch2_out_data ),      // Inport
351
        .in_sof ( ch2_out_sof ),        // Inport
352
        .in_eof ( ch2_out_eof ),        // Inport
353
        .in_src_rdy ( ch2_out_src_rdy ),        // Inport
354
        .out_dst_rdy ( ch2_in_dst_rdy ),        // Outport
355
 
356
        // Outputs:
357
        .out_data ( ch2_in_data ),      // Outport
358
        .out_sof ( ch2_in_sof ),        // Outport
359
        .out_eof ( ch2_in_eof ),        // Outport
360
        .out_src_rdy ( ch2_in_src_rdy ),        // Outport
361
        .in_dst_rdy ( ch2_out_dst_rdy ) // Inport
362
);
363
 
364
// LED Status
365
//moving_led pr_mod_inst (
366
//      .clk(clk_local),
367
//      .rst(reset_cpu_p),
368
//      .leds(LEDS)
369
//);
370
 
371
assign ch3_in_sof = icap_out_sof;
372
assign ch3_in_eof = icap_out_eof;
373
assign ch3_in_src_rdy = icap_out_src_rdy;
374
assign ch3_in_data = icap_dataout;
375
assign ch3_out_dst_rdy = icap_in_dst_rdy;
376
assign icap_datain = ch3_out_data | ch4_out_data;
377
assign icap_out_dst_rdy = ch3_in_dst_rdy | ch4_in_dst_rdy;
378
assign icap_in_src_rdy = ch3_out_src_rdy | ch4_out_src_rdy;
379
assign icap_in_sof = ch3_out_sof | ch4_out_sof;
380
assign icap_in_eof = ch3_out_eof | ch4_out_eof;
381
 
382
assign ch4_in_sof = icap_out_sof;
383
assign ch4_in_eof = icap_out_eof;
384
assign ch4_in_src_rdy = icap_out_src_rdy;
385
assign ch4_in_data = icap_dataout;
386
assign ch4_out_dst_rdy = icap_in_dst_rdy;
387
 
388
assign ch1_in_sof = 1;
389
assign ch1_in_eof = 1;
390
assign ch1_in_src_rdy = 1;
391
assign ch1_out_dst_rdy = 1;
392
assign ch1_in_data = DIP_r;
393
assign LEDnext = ch1_out_data;
394
 
395
 
396
 
397
endmodule

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