OpenCores
URL https://opencores.org/ocsvn/fpga-cf/fpga-cf/trunk

Subversion Repositories fpga-cf

[/] [fpga-cf/] [trunk/] [tools/] [ChannelInterfaceGenerator/] [chifgen.py] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 peteralieb 
# Channel Interface Generator
2 
 
3 
import sys
4 
 
5 
if (len(sys.argv) < 2):
6 
        print 'Usage: chifgen <#channels>'
7 
        exit()
8 
 
9 
numChannels = int(sys.argv[1])
10 
 
11 
if (numChannels < 1):
12 
        print 'Must have one or more channels'
13 
        exit()
14 
 
15 
f = open('channelif.v', 'w')
16 
 
17 
f.write('''// FCP Channel Interface
18 
 
19 
module channelif
20 
(
21 
        // To ethernet platform
22 
        input                                   in_sof,
23 
        input                                   in_eof,
24 
        input                                   in_src_rdy,
25 
        output                          in_dst_rdy,
26 
        input           [7:0]           in_data,
27 
        input           [3:0]           inport_addr,
28 
        output                          out_sof,
29 
        output                          out_eof,
30 
        output                          out_src_rdy,
31 
        input                                   out_dst_rdy,
32 
        output  [7:0]           out_data,
33 
        input           [3:0]           outport_addr,
34 
        ''')
35 
 
36 
for channel in range(1,numChannels+1):
37 
        f.write('''// Channel {0:d}
38 
        input                                   ch{0:d}_in_sof,
39 
        input                                   ch{0:d}_in_eof,
40 
        input                                   ch{0:d}_in_src_rdy,
41 
        output                          ch{0:d}_in_dst_rdy,
42 
        input           [7:0]           ch{0:d}_in_data,
43 
        output                          ch{0:d}_out_sof,
44 
        output                          ch{0:d}_out_eof,
45 
        output                          ch{0:d}_out_src_rdy,
46 
        input                                   ch{0:d}_out_dst_rdy,
47 
        output  [7:0]           ch{0:d}_out_data,
48 
        output                          ch{0:d}_wen,
49 
        output                          ch{0:d}_ren,
50 
        '''.format(channel))
51 
 
52 
f.write('''
53 
        // To user logic
54 
        output  [15:0]  wenables,
55 
        output  [15:0]  renables
56 
);
57 
 
58 
//-------------------------------------------------------------------------------------
59 
//-------------------------------------------------------------------------------------
60 
//                                          Channel-Enable Decoders
61 
//-------------------------------------------------------------------------------------
62 
//-------------------------------------------------------------------------------------
63 
 
64 
reg [15:0]              wenables_i;
65 
reg [15:0]              renables_i;
66 
 
67 
always @(inport_addr)
68 
begin
69 
        case (inport_addr)
70 
                4'h0 : wenables_i = 16'b0000000000000001;
71 
                4'h1 : wenables_i = 16'b0000000000000010;
72 
                4'h2 : wenables_i = 16'b0000000000000100;
73 
                4'h3 : wenables_i = 16'b0000000000001000;
74 
                4'h4 : wenables_i = 16'b0000000000010000;
75 
                4'h5 : wenables_i = 16'b0000000000100000;
76 
                4'h6 : wenables_i = 16'b0000000001000000;
77 
                4'h7 : wenables_i = 16'b0000000010000000;
78 
                4'h8 : wenables_i = 16'b0000000100000000;
79 
                4'h9 : wenables_i = 16'b0000001000000000;
80 
                4'hA : wenables_i = 16'b0000010000000000;
81 
                4'hB : wenables_i = 16'b0000100000000000;
82 
                4'hC : wenables_i = 16'b0001000000000000;
83 
                4'hD : wenables_i = 16'b0010000000000000;
84 
                4'hE : wenables_i = 16'b0100000000000000;
85 
                4'hF : wenables_i = 16'b1000000000000000;
86 
                default: wenables_i = 16'b0000000000000000;
87 
        endcase
88 
end
89 
 
90 
always @(outport_addr)
91 
begin
92 
        case (outport_addr)
93 
                4'h0 : renables_i = 16'b0000000000000001;
94 
                4'h1 : renables_i = 16'b0000000000000010;
95 
                4'h2 : renables_i = 16'b0000000000000100;
96 
                4'h3 : renables_i = 16'b0000000000001000;
97 
                4'h4 : renables_i = 16'b0000000000010000;
98 
                4'h5 : renables_i = 16'b0000000000100000;
99 
                4'h6 : renables_i = 16'b0000000001000000;
100 
                4'h7 : renables_i = 16'b0000000010000000;
101 
                4'h8 : renables_i = 16'b0000000100000000;
102 
                4'h9 : renables_i = 16'b0000001000000000;
103 
                4'hA : renables_i = 16'b0000010000000000;
104 
                4'hB : renables_i = 16'b0000100000000000;
105 
                4'hC : renables_i = 16'b0001000000000000;
106 
                4'hD : renables_i = 16'b0010000000000000;
107 
                4'hE : renables_i = 16'b0100000000000000;
108 
                4'hF : renables_i = 16'b1000000000000000;
109 
                default: renables_i = 16'b0000000000000000;
110 
        endcase
111 
end
112 
 
113 
assign wenables = wenables_i;
114 
assign renables = renables_i;
115 
 
116 
 
117 
//-------------------------------------------------------------------------------------
118 
//-------------------------------------------------------------------------------------
119 
//                                          Multiplexers
120 
//-------------------------------------------------------------------------------------
121 
//-------------------------------------------------------------------------------------
122 
 
123 
 
124 
assign in_dst_rdy = (ch1_wen & ch1_out_dst_rdy)''')
125 
for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_wen & ch{0:d}_out_dst_rdy)'.format(channel))
126 
f.write(''';
127 
assign out_sof = (ch1_ren & ch1_in_sof)''')
128 
for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_ren & ch{0:d}_in_sof)'.format(channel))
129 
f.write(''';
130 
assign out_eof = (ch1_ren & ch1_in_eof)''')
131 
for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_ren & ch{0:d}_in_eof)'.format(channel))
132 
f.write(''';
133 
assign out_src_rdy = (ch1_ren & ch1_in_src_rdy)''')
134 
for channel in range(2, numChannels+1): f.write(' | (ch{0:d}_ren & ch{0:d}_in_src_rdy)'.format(channel))
135 
f.write(''';
136 
assign out_data = ({8{ch1_ren}} & ch1_in_data)''')
137 
for channel in range(2, numChannels+1): f.write(' | ({{8{{ch{0:d}_ren}}}} & ch{0:d}_in_data)'.format(channel))
138 
f.write(''';
139 
 
140 
//-------------------------------------------------------------------------------------
141 
//-------------------------------------------------------------------------------------
142 
//                                          Passthroughs
143 
//-------------------------------------------------------------------------------------
144 
//-------------------------------------------------------------------------------------
145 
''')
146 
for channel in range(1, numChannels+1): f.write('''
147 
assign ch{0:d}_in_dst_rdy = out_dst_rdy;
148 
assign ch{0:d}_out_src_rdy = in_src_rdy;
149 
assign ch{0:d}_out_sof = in_sof;
150 
assign ch{0:d}_out_eof = in_eof;
151 
assign ch{0:d}_out_data = in_data;
152 
assign ch{0:d}_wen = wenables_i[{0:d}];
153 
assign ch{0:d}_ren = renables_i[{0:d}];
154 
'''.format(channel))
155 
f.write('''
156 
endmodule
157 
''')

powered by: WebSVN 2.1.0

© copyright 1999-2026 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.