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[/] [fpga-median/] [trunk/] [rtl/] [median.v] - Blame information for rev 2

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// +----------------------------------------------------------------------------
// Universidade Federal da Bahia
//------------------------------------------------------------------------------
// PROJECT: FPGA Median Filter
//------------------------------------------------------------------------------
// FILE NAME            : median.v
// AUTHOR               : João Carlos Bittencourt
// AUTHOR'S E-MAIL      : joaocarlos@ieee.org
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION  DATE        AUTHOR        DESCRIPTION
// 1.0      2013-08-13  joao.nunes    initial version
// -----------------------------------------------------------------------------
// KEYWORDS: median, filter, image processing
// -----------------------------------------------------------------------------
// PURPOSE: Top level entity of the Median Filter algorithm datapath.
// -----------------------------------------------------------------------------
`define DEBUG
 
module median
#(
    parameter MEM_DATA_WIDTH = 32,
    parameter LUT_ADDR_WIDTH = 10, // Input LUTs
    parameter MEM_ADDR_WIDTH = 10, // Output Memory
    parameter PIXEL_DATA_WIDTH = 8,
    parameter IMG_WIDTH  = 320,
    parameter IMG_HEIGHT = 320
)(
    input clk, // Clock
    input rst_n, // Asynchronous reset active low
    input [31:0] word0,
    input [31:0] word1,
    input [31:0] word2,
 
    // Test signals
    `ifdef DEBUG
    output [PIXEL_DATA_WIDTH-1:0] pixel1,
    output [PIXEL_DATA_WIDTH-1:0] pixel2,
    output [PIXEL_DATA_WIDTH-1:0] pixel3,
    output [PIXEL_DATA_WIDTH-1:0] pixel4,
    `else
    output [MEM_DATA_WIDTH-1:0] median_word,
    `endif
    output [LUT_ADDR_WIDTH-1:0] raddr_a,
    output [LUT_ADDR_WIDTH-1:0] raddr_b,
    output [LUT_ADDR_WIDTH-1:0] raddr_c,
 
    output [MEM_ADDR_WIDTH-1:0] waddr
);
 
    wire [PIXEL_DATA_WIDTH-1:0] x2_y1;
    wire [PIXEL_DATA_WIDTH-1:0] x2_y0;
    wire [PIXEL_DATA_WIDTH-1:0] x2_ym1;
    wire [PIXEL_DATA_WIDTH-1:0] x1_y1;
    wire [PIXEL_DATA_WIDTH-1:0] x1_y0;
    wire [PIXEL_DATA_WIDTH-1:0] x1_ym1;
    wire [PIXEL_DATA_WIDTH-1:0] x0_y1;
    wire [PIXEL_DATA_WIDTH-1:0] x0_y0;
    wire [PIXEL_DATA_WIDTH-1:0] x0_ym1;
    wire [PIXEL_DATA_WIDTH-1:0] xm1_y1;
    wire [PIXEL_DATA_WIDTH-1:0] xm1_y0;
    wire [PIXEL_DATA_WIDTH-1:0] xm1_ym1;
 
    assign x2_y1   = word0[PIXEL_DATA_WIDTH-1:0];
    assign x2_y0   = word1[PIXEL_DATA_WIDTH-1:0];
    assign x2_ym1  = word2[PIXEL_DATA_WIDTH-1:0];
 
    assign x1_y1   = word0[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
    assign x1_y0   = word1[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
    assign x1_ym1  = word2[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
 
    assign x0_y1   = word0[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
    assign x0_y0   = word1[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
    assign x0_ym1  = word2[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
 
    assign xm1_y1  = word0[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
    assign xm1_y0  = word1[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
    assign xm1_ym1 = word2[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
 
    // wire [PIXEL_DATA_WIDTH-1:0] pixel1_sig;
    // wire [PIXEL_DATA_WIDTH-1:0] pixel2_sig;
    // wire [PIXEL_DATA_WIDTH-1:0] pixel3_sig;
    // wire [PIXEL_DATA_WIDTH-1:0] pixel4_sig;
 
    `ifndef DEBUG
    assign median_word = {pixel1,pixel2,pixel3,pixel4};
    `endif
 
    // Common network output signals
    wire [PIXEL_DATA_WIDTH-1:0] c3l;
    wire [PIXEL_DATA_WIDTH-1:0] c3h;
    wire [PIXEL_DATA_WIDTH-1:0] c3m;
    wire [PIXEL_DATA_WIDTH-1:0] c3l_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c3h_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c3m_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c2l;
    wire [PIXEL_DATA_WIDTH-1:0] c2h;
    wire [PIXEL_DATA_WIDTH-1:0] c2m;
    wire [PIXEL_DATA_WIDTH-1:0] c2l_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c2h_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c2m_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c1l;
    wire [PIXEL_DATA_WIDTH-1:0] c1h;
    wire [PIXEL_DATA_WIDTH-1:0] c1m;
    wire [PIXEL_DATA_WIDTH-1:0] c0h;
    wire [PIXEL_DATA_WIDTH-1:0] c0m;
    wire [PIXEL_DATA_WIDTH-1:0] c0l;
 
    // Delay signals to be placed over the output registers
    wire [PIXEL_DATA_WIDTH-1:0] p1_sig;
    wire [PIXEL_DATA_WIDTH-1:0] p2_sig;
    wire [PIXEL_DATA_WIDTH-1:0] p3_sig;
 
    //------------------------------------------------------------
    // Windowing Memory Address Controller
    //------------------------------------------------------------
    state_machine
    #(
        .LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),
        .IMG_WIDTH(IMG_WIDTH),
        .IMG_HEIGHT(IMG_HEIGHT)
    ) window_contol (
        .clk(clk), // Clock
        .rst_n(rst_n), // Asynchronous reset active low
 
        .raddr_a(raddr_a),
        .raddr_b(raddr_b),
        .raddr_c(raddr_c),
 
        .waddr(waddr)
    );
 
    //------------------------------------------------------------
    // Pixel registers
    //------------------------------------------------------------
    // always @(posedge clk or negedge rst_n)
    // begin : pixel_reg
    //     if(~rst_n) begin
    //         pixel1 <= {PIXEL_DATA_WIDTH{1'b0}};
    //         pixel2 <= {PIXEL_DATA_WIDTH{1'b0}};
    //         pixel3 <= {PIXEL_DATA_WIDTH{1'b0}};
    //         pixel4 <= {PIXEL_DATA_WIDTH{1'b0}};
    //     end else begin
    //         pixel1 <= pixel1_sig;
    //         pixel2 <= pixel2_sig;
    //         pixel3 <= pixel3_sig;
    //         //pixel4 <= pixel4_sig;
    //    end
    // end
 
    //------------------------------------------------------------
    // Input datapath common network
    //------------------------------------------------------------
    common_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) common_network_u0 (
        .x2_y1(x2_y1),
        .x2_y0(x2_y0),
        .x2_ym1(x2_ym1),
        .x1_y1(x1_y1),
        .x1_y0(x1_y0),
        .x1_ym1(x1_ym1),
        .x0_y1(x0_y1),
        .x0_y0(x0_y0),
        .x0_ym1(x0_ym1),
        .xm1_y1(xm1_y1),
        .xm1_y0(xm1_y0),
        .xm1_ym1(xm1_ym1),
 
        .c3l(c3l),
        .c3h(c3h),
        .c3m(c3m),
        .c2l(c2l),
        .c2h(c2h),
        .c2m(c2m),
        .c1l(c1l),
        .c1h(c1h),
        .c1m(c1m),
        .c0h(c0h),
        .c0m(c0m),
        .c0l(c0l)
    );
 
    //------------------------------------------------------------
    // Pipeline Registers
    //------------------------------------------------------------
    dff_3_pipe
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) dff_c3_pipe (
        .clk(clk),
        .rst_n(rst_n),
        .d0(c3h),
        .d1(c3m),
        .d2(c3l),
 
        .q0(c3h_reg),
        .q1(c3m_reg),
        .q2(c3l_reg)
    );
 
    dff_3_pipe
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) dff_c2_pipe (
        .clk(clk),
        .rst_n(rst_n),
        .d0(c2h),
        .d1(c2m),
        .d2(c2l),
 
        .q0(c2h_reg),
        .q1(c2m_reg),
        .q2(c2l_reg)
    );
 
    // Output pieline registers (P1, P2, P3)
    dff_3_pipe
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) dff_out_pipe (
        .clk(clk),
        .rst_n(rst_n),
        .d0(p1_sig),
        .d1(p2_sig),
        .d2(p3_sig),
 
        .q0(pixel1),
        .q1(pixel2),
        .q2(pixel3)
    );
 
    //------------------------------------------------------------
    // Median Filter Pixel Network
    //------------------------------------------------------------
 
    // Pixel 1
    pixel_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) pixel_network_u0 (
        .c3h(c1h),
        .c3m(c1m),
        .c3l(c1l),
        .c2h(c0h),
        .c2m(c0m),
        .c2l(c0l),
        .c1h(c3h_reg),
        .c1m(c3m_reg),
        .c1l(c3l_reg),
 
        .median(p1_sig)
    );
 
    pixel_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) pixel_network_u1 (
        .c3h(c2h),
        .c3m(c2m),
        .c3l(c2l),
        .c2h(c1h),
        .c2m(c1m),
        .c2l(c1l),
        .c1h(c0h),
        .c1m(c0m),
        .c1l(c0l),
 
        .median(p2_sig)
    );
 
    pixel_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) pixel_network_u2 (
        .c3h(c3h),
        .c3m(c3m),
        .c3l(c3l),
        .c2h(c2h),
        .c2m(c2m),
        .c2l(c2l),
        .c1h(c1h),
        .c1m(c1m),
        .c1l(c1l),
 
        .median(p3_sig)
    );
 
    pixel_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) pixel_network_u3 (
        .c3h(c0h),
        .c3m(c0m),
        .c3l(c0l),
        .c2h(c3h_reg),
        .c2m(c3m_reg),
        .c2l(c3l_reg),
        .c1h(c2h_reg),
        .c1m(c2m_reg),
        .c1l(c2l_reg),
 
        .median(pixel4)
    );
 
endmodule

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Subversion Repositories fpga-median

[/] [fpga-median/] [trunk/] [rtl/] [median.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	joaocarlos	`// +----------------------------------------------------------------------------`
2			`// Universidade Federal da Bahia`
3			`//------------------------------------------------------------------------------`
4			`// PROJECT: FPGA Median Filter`
5			`//------------------------------------------------------------------------------`
6			`// FILE NAME : median.v`
7			`// AUTHOR : João Carlos Bittencourt`
8			`// AUTHOR'S E-MAIL : joaocarlos@ieee.org`
9			`// -----------------------------------------------------------------------------`
10			`// RELEASE HISTORY`
11			`// VERSION DATE AUTHOR DESCRIPTION`
12			`// 1.0 2013-08-13 joao.nunes initial version`
13			`// -----------------------------------------------------------------------------`
14			`// KEYWORDS: median, filter, image processing`
15			`// -----------------------------------------------------------------------------`
16			`// PURPOSE: Top level entity of the Median Filter algorithm datapath.`
17			`// -----------------------------------------------------------------------------`
18			`define DEBUG
19
20			`module median`
21			`#(`
22			`parameter MEM_DATA_WIDTH = 32,`
23			`parameter LUT_ADDR_WIDTH = 10, // Input LUTs`
24			`parameter MEM_ADDR_WIDTH = 10, // Output Memory`
25			`parameter PIXEL_DATA_WIDTH = 8,`
26			`parameter IMG_WIDTH = 320,`
27			`parameter IMG_HEIGHT = 320`
28			`)(`
29			`input clk, // Clock`
30			`input rst_n, // Asynchronous reset active low`
31			`input [31:0] word0,`
32			`input [31:0] word1,`
33			`input [31:0] word2,`
34
35			`// Test signals`
36			`ifdef DEBUG
37			`output [PIXEL_DATA_WIDTH-1:0] pixel1,`
38			`output [PIXEL_DATA_WIDTH-1:0] pixel2,`
39			`output [PIXEL_DATA_WIDTH-1:0] pixel3,`
40			`output [PIXEL_DATA_WIDTH-1:0] pixel4,`
41			`else
42			`output [MEM_DATA_WIDTH-1:0] median_word,`
43			`endif
44			`output [LUT_ADDR_WIDTH-1:0] raddr_a,`
45			`output [LUT_ADDR_WIDTH-1:0] raddr_b,`
46			`output [LUT_ADDR_WIDTH-1:0] raddr_c,`
47
48			`output [MEM_ADDR_WIDTH-1:0] waddr`
49			`);`
50
51			`wire [PIXEL_DATA_WIDTH-1:0] x2_y1;`
52			`wire [PIXEL_DATA_WIDTH-1:0] x2_y0;`
53			`wire [PIXEL_DATA_WIDTH-1:0] x2_ym1;`
54			`wire [PIXEL_DATA_WIDTH-1:0] x1_y1;`
55			`wire [PIXEL_DATA_WIDTH-1:0] x1_y0;`
56			`wire [PIXEL_DATA_WIDTH-1:0] x1_ym1;`
57			`wire [PIXEL_DATA_WIDTH-1:0] x0_y1;`
58			`wire [PIXEL_DATA_WIDTH-1:0] x0_y0;`
59			`wire [PIXEL_DATA_WIDTH-1:0] x0_ym1;`
60			`wire [PIXEL_DATA_WIDTH-1:0] xm1_y1;`
61			`wire [PIXEL_DATA_WIDTH-1:0] xm1_y0;`
62			`wire [PIXEL_DATA_WIDTH-1:0] xm1_ym1;`
63
64			`assign x2_y1 = word0[PIXEL_DATA_WIDTH-1:0];`
65			`assign x2_y0 = word1[PIXEL_DATA_WIDTH-1:0];`
66			`assign x2_ym1 = word2[PIXEL_DATA_WIDTH-1:0];`
67
68			`assign x1_y1 = word0[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];`
69			`assign x1_y0 = word1[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];`
70			`assign x1_ym1 = word2[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];`
71
72			`assign x0_y1 = word0[(PIXEL_DATA_WIDTH3)-1:(PIXEL_DATA_WIDTH2)];`
73			`assign x0_y0 = word1[(PIXEL_DATA_WIDTH3)-1:(PIXEL_DATA_WIDTH2)];`
74			`assign x0_ym1 = word2[(PIXEL_DATA_WIDTH3)-1:(PIXEL_DATA_WIDTH2)];`
75
76			`assign xm1_y1 = word0[(PIXEL_DATA_WIDTH4)-1:(PIXEL_DATA_WIDTH3)];`
77			`assign xm1_y0 = word1[(PIXEL_DATA_WIDTH4)-1:(PIXEL_DATA_WIDTH3)];`
78			`assign xm1_ym1 = word2[(PIXEL_DATA_WIDTH4)-1:(PIXEL_DATA_WIDTH3)];`
79
80			`// wire [PIXEL_DATA_WIDTH-1:0] pixel1_sig;`
81			`// wire [PIXEL_DATA_WIDTH-1:0] pixel2_sig;`
82			`// wire [PIXEL_DATA_WIDTH-1:0] pixel3_sig;`
83			`// wire [PIXEL_DATA_WIDTH-1:0] pixel4_sig;`
84
85			`ifndef DEBUG
86			`assign median_word = {pixel1,pixel2,pixel3,pixel4};`
87			`endif
88
89			`// Common network output signals`
90			`wire [PIXEL_DATA_WIDTH-1:0] c3l;`
91			`wire [PIXEL_DATA_WIDTH-1:0] c3h;`
92			`wire [PIXEL_DATA_WIDTH-1:0] c3m;`
93			`wire [PIXEL_DATA_WIDTH-1:0] c3l_reg;`
94			`wire [PIXEL_DATA_WIDTH-1:0] c3h_reg;`
95			`wire [PIXEL_DATA_WIDTH-1:0] c3m_reg;`
96			`wire [PIXEL_DATA_WIDTH-1:0] c2l;`
97			`wire [PIXEL_DATA_WIDTH-1:0] c2h;`
98			`wire [PIXEL_DATA_WIDTH-1:0] c2m;`
99			`wire [PIXEL_DATA_WIDTH-1:0] c2l_reg;`
100			`wire [PIXEL_DATA_WIDTH-1:0] c2h_reg;`
101			`wire [PIXEL_DATA_WIDTH-1:0] c2m_reg;`
102			`wire [PIXEL_DATA_WIDTH-1:0] c1l;`
103			`wire [PIXEL_DATA_WIDTH-1:0] c1h;`
104			`wire [PIXEL_DATA_WIDTH-1:0] c1m;`
105			`wire [PIXEL_DATA_WIDTH-1:0] c0h;`
106			`wire [PIXEL_DATA_WIDTH-1:0] c0m;`
107			`wire [PIXEL_DATA_WIDTH-1:0] c0l;`
108
109			`// Delay signals to be placed over the output registers`
110			`wire [PIXEL_DATA_WIDTH-1:0] p1_sig;`
111			`wire [PIXEL_DATA_WIDTH-1:0] p2_sig;`
112			`wire [PIXEL_DATA_WIDTH-1:0] p3_sig;`
113
114			`//------------------------------------------------------------`
115			`// Windowing Memory Address Controller`
116			`//------------------------------------------------------------`
117			`state_machine`
118			`#(`
119			`.LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),`
120			`.IMG_WIDTH(IMG_WIDTH),`
121			`.IMG_HEIGHT(IMG_HEIGHT)`
122			`) window_contol (`
123			`.clk(clk), // Clock`
124			`.rst_n(rst_n), // Asynchronous reset active low`
125
126			`.raddr_a(raddr_a),`
127			`.raddr_b(raddr_b),`
128			`.raddr_c(raddr_c),`
129
130			`.waddr(waddr)`
131			`);`
132
133			`//------------------------------------------------------------`
134			`// Pixel registers`
135			`//------------------------------------------------------------`
136			`// always @(posedge clk or negedge rst_n)`
137			`// begin : pixel_reg`
138			`// if(~rst_n) begin`
139			`// pixel1 <= {PIXEL_DATA_WIDTH{1'b0}};`
140			`// pixel2 <= {PIXEL_DATA_WIDTH{1'b0}};`
141			`// pixel3 <= {PIXEL_DATA_WIDTH{1'b0}};`
142			`// pixel4 <= {PIXEL_DATA_WIDTH{1'b0}};`
143			`// end else begin`
144			`// pixel1 <= pixel1_sig;`
145			`// pixel2 <= pixel2_sig;`
146			`// pixel3 <= pixel3_sig;`
147			`// //pixel4 <= pixel4_sig;`
148			`// end`
149			`// end`
150
151			`//------------------------------------------------------------`
152			`// Input datapath common network`
153			`//------------------------------------------------------------`
154			`common_network`
155			`#(`
156			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
157			`) common_network_u0 (`
158			`.x2_y1(x2_y1),`
159			`.x2_y0(x2_y0),`
160			`.x2_ym1(x2_ym1),`
161			`.x1_y1(x1_y1),`
162			`.x1_y0(x1_y0),`
163			`.x1_ym1(x1_ym1),`
164			`.x0_y1(x0_y1),`
165			`.x0_y0(x0_y0),`
166			`.x0_ym1(x0_ym1),`
167			`.xm1_y1(xm1_y1),`
168			`.xm1_y0(xm1_y0),`
169			`.xm1_ym1(xm1_ym1),`
170
171			`.c3l(c3l),`
172			`.c3h(c3h),`
173			`.c3m(c3m),`
174			`.c2l(c2l),`
175			`.c2h(c2h),`
176			`.c2m(c2m),`
177			`.c1l(c1l),`
178			`.c1h(c1h),`
179			`.c1m(c1m),`
180			`.c0h(c0h),`
181			`.c0m(c0m),`
182			`.c0l(c0l)`
183			`);`
184
185			`//------------------------------------------------------------`
186			`// Pipeline Registers`
187			`//------------------------------------------------------------`
188			`dff_3_pipe`
189			`#(`
190			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
191			`) dff_c3_pipe (`
192			`.clk(clk),`
193			`.rst_n(rst_n),`
194			`.d0(c3h),`
195			`.d1(c3m),`
196			`.d2(c3l),`
197
198			`.q0(c3h_reg),`
199			`.q1(c3m_reg),`
200			`.q2(c3l_reg)`
201			`);`
202
203			`dff_3_pipe`
204			`#(`
205			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
206			`) dff_c2_pipe (`
207			`.clk(clk),`
208			`.rst_n(rst_n),`
209			`.d0(c2h),`
210			`.d1(c2m),`
211			`.d2(c2l),`
212
213			`.q0(c2h_reg),`
214			`.q1(c2m_reg),`
215			`.q2(c2l_reg)`
216			`);`
217
218			`// Output pieline registers (P1, P2, P3)`
219			`dff_3_pipe`
220			`#(`
221			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
222			`) dff_out_pipe (`
223			`.clk(clk),`
224			`.rst_n(rst_n),`
225			`.d0(p1_sig),`
226			`.d1(p2_sig),`
227			`.d2(p3_sig),`
228
229			`.q0(pixel1),`
230			`.q1(pixel2),`
231			`.q2(pixel3)`
232			`);`
233
234			`//------------------------------------------------------------`
235			`// Median Filter Pixel Network`
236			`//------------------------------------------------------------`
237
238			`// Pixel 1`
239			`pixel_network`
240			`#(`
241			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
242			`) pixel_network_u0 (`
243			`.c3h(c1h),`
244			`.c3m(c1m),`
245			`.c3l(c1l),`
246			`.c2h(c0h),`
247			`.c2m(c0m),`
248			`.c2l(c0l),`
249			`.c1h(c3h_reg),`
250			`.c1m(c3m_reg),`
251			`.c1l(c3l_reg),`
252
253			`.median(p1_sig)`
254			`);`
255
256			`pixel_network`
257			`#(`
258			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
259			`) pixel_network_u1 (`
260			`.c3h(c2h),`
261			`.c3m(c2m),`
262			`.c3l(c2l),`
263			`.c2h(c1h),`
264			`.c2m(c1m),`
265			`.c2l(c1l),`
266			`.c1h(c0h),`
267			`.c1m(c0m),`
268			`.c1l(c0l),`
269
270			`.median(p2_sig)`
271			`);`
272
273			`pixel_network`
274			`#(`
275			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
276			`) pixel_network_u2 (`
277			`.c3h(c3h),`
278			`.c3m(c3m),`
279			`.c3l(c3l),`
280			`.c2h(c2h),`
281			`.c2m(c2m),`
282			`.c2l(c2l),`
283			`.c1h(c1h),`
284			`.c1m(c1m),`
285			`.c1l(c1l),`
286
287			`.median(p3_sig)`
288			`);`
289
290			`pixel_network`
291			`#(`
292			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
293			`) pixel_network_u3 (`
294			`.c3h(c0h),`
295			`.c3m(c0m),`
296			`.c3l(c0l),`
297			`.c2h(c3h_reg),`
298			`.c2m(c3m_reg),`
299			`.c2l(c3l_reg),`
300			`.c1h(c2h_reg),`
301			`.c1m(c2m_reg),`
302			`.c1l(c2l_reg),`
303
304			`.median(pixel4)`
305			`);`
306
307			`endmodule`