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[/] [fpga-median/] [trunk/] [rtl/] [median.v] - Blame information for rev 9

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/* --------------------------------------------------------------------------------
 This file is part of FPGA Median Filter.
 
    FPGA Median Filter is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.
 
    FPGA Median Filter is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
 
    You should have received a copy of the GNU General Public License
    along with FPGA Median Filter.  If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------- */
/* +----------------------------------------------------------------------------
   Universidade Federal da Bahia
  ------------------------------------------------------------------------------
   PROJECT: FPGA Median Filter
  ------------------------------------------------------------------------------
   FILE NAME            : median.v
   AUTHOR               : João Carlos Bittencourt
   AUTHOR'S E-MAIL      : joaocarlos@ieee.org
   -----------------------------------------------------------------------------
   RELEASE HISTORY
   VERSION  DATE        AUTHOR        DESCRIPTION
   1.0      2013-08-13  joao.nunes    initial version
   -----------------------------------------------------------------------------
   KEYWORDS: median, filter, image processing
   -----------------------------------------------------------------------------
   PURPOSE: Top level entity of the Median Filter algorithm datapath.
   ----------------------------------------------------------------------------- */
`define DEBUG
 
module median
#(
    parameter MEM_DATA_WIDTH = 32,
    parameter LUT_ADDR_WIDTH = 10, // Input LUTs
    parameter MEM_ADDR_WIDTH = 10, // Output Memory
    parameter PIXEL_DATA_WIDTH = 8,
    parameter IMG_WIDTH  = 320,
    parameter IMG_HEIGHT = 320
)(
    input clk, // Clock
    input rst_n, // Asynchronous reset active low
    input [31:0] word0,
    input [31:0] word1,
    input [31:0] word2,
 
    // Test signals
    `ifdef DEBUG
    output [PIXEL_DATA_WIDTH-1:0] pixel1,
    output [PIXEL_DATA_WIDTH-1:0] pixel2,
    output [PIXEL_DATA_WIDTH-1:0] pixel3,
    output [PIXEL_DATA_WIDTH-1:0] pixel4,
    `else
    output [MEM_DATA_WIDTH-1:0] median_word,
    `endif
    output [LUT_ADDR_WIDTH-1:0] raddr_a,
    output [LUT_ADDR_WIDTH-1:0] raddr_b,
    output [LUT_ADDR_WIDTH-1:0] raddr_c,
 
    output [MEM_ADDR_WIDTH-1:0] waddr
);
 
    wire [PIXEL_DATA_WIDTH-1:0] x2_y1;
    wire [PIXEL_DATA_WIDTH-1:0] x2_y0;
    wire [PIXEL_DATA_WIDTH-1:0] x2_ym1;
    wire [PIXEL_DATA_WIDTH-1:0] x1_y1;
    wire [PIXEL_DATA_WIDTH-1:0] x1_y0;
    wire [PIXEL_DATA_WIDTH-1:0] x1_ym1;
    wire [PIXEL_DATA_WIDTH-1:0] x0_y1;
    wire [PIXEL_DATA_WIDTH-1:0] x0_y0;
    wire [PIXEL_DATA_WIDTH-1:0] x0_ym1;
    wire [PIXEL_DATA_WIDTH-1:0] xm1_y1;
    wire [PIXEL_DATA_WIDTH-1:0] xm1_y0;
    wire [PIXEL_DATA_WIDTH-1:0] xm1_ym1;
 
    assign x2_y1   = word0[PIXEL_DATA_WIDTH-1:0];
    assign x2_y0   = word1[PIXEL_DATA_WIDTH-1:0];
    assign x2_ym1  = word2[PIXEL_DATA_WIDTH-1:0];
 
    assign x1_y1   = word0[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
    assign x1_y0   = word1[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
    assign x1_ym1  = word2[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];
 
    assign x0_y1   = word0[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
    assign x0_y0   = word1[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
    assign x0_ym1  = word2[(PIXEL_DATA_WIDTH*3)-1:(PIXEL_DATA_WIDTH*2)];
 
    assign xm1_y1  = word0[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
    assign xm1_y0  = word1[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
    assign xm1_ym1 = word2[(PIXEL_DATA_WIDTH*4)-1:(PIXEL_DATA_WIDTH*3)];
 
    // wire [PIXEL_DATA_WIDTH-1:0] pixel1_sig;
    // wire [PIXEL_DATA_WIDTH-1:0] pixel2_sig;
    // wire [PIXEL_DATA_WIDTH-1:0] pixel3_sig;
    // wire [PIXEL_DATA_WIDTH-1:0] pixel4_sig;
 
    `ifndef DEBUG
    assign median_word = {pixel1,pixel2,pixel3,pixel4};
    `endif
 
    // Common network output signals
    wire [PIXEL_DATA_WIDTH-1:0] c3l;
    wire [PIXEL_DATA_WIDTH-1:0] c3h;
    wire [PIXEL_DATA_WIDTH-1:0] c3m;
    wire [PIXEL_DATA_WIDTH-1:0] c3l_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c3h_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c3m_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c2l;
    wire [PIXEL_DATA_WIDTH-1:0] c2h;
    wire [PIXEL_DATA_WIDTH-1:0] c2m;
    wire [PIXEL_DATA_WIDTH-1:0] c2l_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c2h_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c2m_reg;
    wire [PIXEL_DATA_WIDTH-1:0] c1l;
    wire [PIXEL_DATA_WIDTH-1:0] c1h;
    wire [PIXEL_DATA_WIDTH-1:0] c1m;
    wire [PIXEL_DATA_WIDTH-1:0] c0h;
    wire [PIXEL_DATA_WIDTH-1:0] c0m;
    wire [PIXEL_DATA_WIDTH-1:0] c0l;
 
    // Delay signals to be placed over the output registers
    wire [PIXEL_DATA_WIDTH-1:0] p1_sig;
    wire [PIXEL_DATA_WIDTH-1:0] p2_sig;
    wire [PIXEL_DATA_WIDTH-1:0] p3_sig;
 
    //------------------------------------------------------------
    // Windowing Memory Address Controller
    //------------------------------------------------------------
    state_machine
    #(
        .LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),
        .IMG_WIDTH(IMG_WIDTH),
        .IMG_HEIGHT(IMG_HEIGHT)
    ) window_contol (
        .clk(clk), // Clock
        .rst_n(rst_n), // Asynchronous reset active low
 
        .raddr_a(raddr_a),
        .raddr_b(raddr_b),
        .raddr_c(raddr_c),
 
        .waddr(waddr)
    );
 
    //------------------------------------------------------------
    // Pixel registers
    //------------------------------------------------------------
    // always @(posedge clk or negedge rst_n)
    // begin : pixel_reg
    //     if(~rst_n) begin
    //         pixel1 <= {PIXEL_DATA_WIDTH{1'b0}};
    //         pixel2 <= {PIXEL_DATA_WIDTH{1'b0}};
    //         pixel3 <= {PIXEL_DATA_WIDTH{1'b0}};
    //         pixel4 <= {PIXEL_DATA_WIDTH{1'b0}};
    //     end else begin
    //         pixel1 <= pixel1_sig;
    //         pixel2 <= pixel2_sig;
    //         pixel3 <= pixel3_sig;
    //         //pixel4 <= pixel4_sig;
    //    end
    // end
 
    //------------------------------------------------------------
    // Input datapath common network
    //------------------------------------------------------------
    common_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) common_network_u0 (
        .x2_y1(x2_y1),
        .x2_y0(x2_y0),
        .x2_ym1(x2_ym1),
        .x1_y1(x1_y1),
        .x1_y0(x1_y0),
        .x1_ym1(x1_ym1),
        .x0_y1(x0_y1),
        .x0_y0(x0_y0),
        .x0_ym1(x0_ym1),
        .xm1_y1(xm1_y1),
        .xm1_y0(xm1_y0),
        .xm1_ym1(xm1_ym1),
 
        .c3l(c3l),
        .c3h(c3h),
        .c3m(c3m),
        .c2l(c2l),
        .c2h(c2h),
        .c2m(c2m),
        .c1l(c1l),
        .c1h(c1h),
        .c1m(c1m),
        .c0h(c0h),
        .c0m(c0m),
        .c0l(c0l)
    );
 
    //------------------------------------------------------------
    // Pipeline Registers
    //------------------------------------------------------------
    dff_3_pipe
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) dff_c3_pipe (
        .clk(clk),
        .rst_n(rst_n),
        .d0(c3h),
        .d1(c3m),
        .d2(c3l),
 
        .q0(c3h_reg),
        .q1(c3m_reg),
        .q2(c3l_reg)
    );
 
    dff_3_pipe
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) dff_c2_pipe (
        .clk(clk),
        .rst_n(rst_n),
        .d0(c2h),
        .d1(c2m),
        .d2(c2l),
 
        .q0(c2h_reg),
        .q1(c2m_reg),
        .q2(c2l_reg)
    );
 
    // Output pieline registers (P1, P2, P3)
    dff_3_pipe
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) dff_out_pipe (
        .clk(clk),
        .rst_n(rst_n),
        .d0(p1_sig),
        .d1(p2_sig),
        .d2(p3_sig),
 
        .q0(pixel1),
        .q1(pixel2),
        .q2(pixel3)
    );
 
    //------------------------------------------------------------
    // Median Filter Pixel Network
    //------------------------------------------------------------
 
    // Pixel 1
    pixel_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) pixel_network_u0 (
        .c3h(c1h),
        .c3m(c1m),
        .c3l(c1l),
        .c2h(c0h),
        .c2m(c0m),
        .c2l(c0l),
        .c1h(c3h_reg),
        .c1m(c3m_reg),
        .c1l(c3l_reg),
 
        .median(p1_sig)
    );
 
    pixel_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) pixel_network_u1 (
        .c3h(c2h),
        .c3m(c2m),
        .c3l(c2l),
        .c2h(c1h),
        .c2m(c1m),
        .c2l(c1l),
        .c1h(c0h),
        .c1m(c0m),
        .c1l(c0l),
 
        .median(p2_sig)
    );
 
    pixel_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) pixel_network_u2 (
        .c3h(c3h),
        .c3m(c3m),
        .c3l(c3l),
        .c2h(c2h),
        .c2m(c2m),
        .c2l(c2l),
        .c1h(c1h),
        .c1m(c1m),
        .c1l(c1l),
 
        .median(p3_sig)
    );
 
    pixel_network
    #(
        .DATA_WIDTH(PIXEL_DATA_WIDTH)
    ) pixel_network_u3 (
        .c3h(c0h),
        .c3m(c0m),
        .c3l(c0l),
        .c2h(c3h_reg),
        .c2m(c3m_reg),
        .c2l(c3l_reg),
        .c1h(c2h_reg),
        .c1m(c2m_reg),
        .c1l(c2l_reg),
 
        .median(pixel4)
    );
 
endmodule

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Subversion Repositories fpga-median

[/] [fpga-median/] [trunk/] [rtl/] [median.v] - Blame information for rev 9

Line No.	Rev	Author	Line
1	9	joaocarlos	`/* --------------------------------------------------------------------------------`
2			`This file is part of FPGA Median Filter.`
3
4			`FPGA Median Filter is free software: you can redistribute it and/or modify`
5			`it under the terms of the GNU General Public License as published by`
6			`the Free Software Foundation, either version 3 of the License, or`
7			`(at your option) any later version.`
8
9			`FPGA Median Filter is distributed in the hope that it will be useful,`
10			`but WITHOUT ANY WARRANTY; without even the implied warranty of`
11			`MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
12			`GNU General Public License for more details.`
13
14			`You should have received a copy of the GNU General Public License`
15			`along with FPGA Median Filter. If not, see <http://www.gnu.org/licenses/>.`
16			`-------------------------------------------------------------------------------- */`
17			`/* +----------------------------------------------------------------------------`
18			`Universidade Federal da Bahia`
19			`------------------------------------------------------------------------------`
20			`PROJECT: FPGA Median Filter`
21			`------------------------------------------------------------------------------`
22			`FILE NAME : median.v`
23			`AUTHOR : João Carlos Bittencourt`
24			`AUTHOR'S E-MAIL : joaocarlos@ieee.org`
25			`-----------------------------------------------------------------------------`
26			`RELEASE HISTORY`
27			`VERSION DATE AUTHOR DESCRIPTION`
28			`1.0 2013-08-13 joao.nunes initial version`
29			`-----------------------------------------------------------------------------`
30			`KEYWORDS: median, filter, image processing`
31			`-----------------------------------------------------------------------------`
32			`PURPOSE: Top level entity of the Median Filter algorithm datapath.`
33			`----------------------------------------------------------------------------- */`
34	2	joaocarlos	`define DEBUG
35
36			`module median`
37			`#(`
38			`parameter MEM_DATA_WIDTH = 32,`
39			`parameter LUT_ADDR_WIDTH = 10, // Input LUTs`
40			`parameter MEM_ADDR_WIDTH = 10, // Output Memory`
41			`parameter PIXEL_DATA_WIDTH = 8,`
42			`parameter IMG_WIDTH = 320,`
43			`parameter IMG_HEIGHT = 320`
44			`)(`
45			`input clk, // Clock`
46			`input rst_n, // Asynchronous reset active low`
47			`input [31:0] word0,`
48			`input [31:0] word1,`
49			`input [31:0] word2,`
50
51			`// Test signals`
52			`ifdef DEBUG
53			`output [PIXEL_DATA_WIDTH-1:0] pixel1,`
54			`output [PIXEL_DATA_WIDTH-1:0] pixel2,`
55			`output [PIXEL_DATA_WIDTH-1:0] pixel3,`
56			`output [PIXEL_DATA_WIDTH-1:0] pixel4,`
57			`else
58			`output [MEM_DATA_WIDTH-1:0] median_word,`
59			`endif
60			`output [LUT_ADDR_WIDTH-1:0] raddr_a,`
61			`output [LUT_ADDR_WIDTH-1:0] raddr_b,`
62			`output [LUT_ADDR_WIDTH-1:0] raddr_c,`
63
64			`output [MEM_ADDR_WIDTH-1:0] waddr`
65			`);`
66
67			`wire [PIXEL_DATA_WIDTH-1:0] x2_y1;`
68			`wire [PIXEL_DATA_WIDTH-1:0] x2_y0;`
69			`wire [PIXEL_DATA_WIDTH-1:0] x2_ym1;`
70			`wire [PIXEL_DATA_WIDTH-1:0] x1_y1;`
71			`wire [PIXEL_DATA_WIDTH-1:0] x1_y0;`
72			`wire [PIXEL_DATA_WIDTH-1:0] x1_ym1;`
73			`wire [PIXEL_DATA_WIDTH-1:0] x0_y1;`
74			`wire [PIXEL_DATA_WIDTH-1:0] x0_y0;`
75			`wire [PIXEL_DATA_WIDTH-1:0] x0_ym1;`
76			`wire [PIXEL_DATA_WIDTH-1:0] xm1_y1;`
77			`wire [PIXEL_DATA_WIDTH-1:0] xm1_y0;`
78			`wire [PIXEL_DATA_WIDTH-1:0] xm1_ym1;`
79
80			`assign x2_y1 = word0[PIXEL_DATA_WIDTH-1:0];`
81			`assign x2_y0 = word1[PIXEL_DATA_WIDTH-1:0];`
82			`assign x2_ym1 = word2[PIXEL_DATA_WIDTH-1:0];`
83
84			`assign x1_y1 = word0[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];`
85			`assign x1_y0 = word1[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];`
86			`assign x1_ym1 = word2[(PIXEL_DATA_WIDTH*2)-1:PIXEL_DATA_WIDTH];`
87
88			`assign x0_y1 = word0[(PIXEL_DATA_WIDTH3)-1:(PIXEL_DATA_WIDTH2)];`
89			`assign x0_y0 = word1[(PIXEL_DATA_WIDTH3)-1:(PIXEL_DATA_WIDTH2)];`
90			`assign x0_ym1 = word2[(PIXEL_DATA_WIDTH3)-1:(PIXEL_DATA_WIDTH2)];`
91
92			`assign xm1_y1 = word0[(PIXEL_DATA_WIDTH4)-1:(PIXEL_DATA_WIDTH3)];`
93			`assign xm1_y0 = word1[(PIXEL_DATA_WIDTH4)-1:(PIXEL_DATA_WIDTH3)];`
94			`assign xm1_ym1 = word2[(PIXEL_DATA_WIDTH4)-1:(PIXEL_DATA_WIDTH3)];`
95
96			`// wire [PIXEL_DATA_WIDTH-1:0] pixel1_sig;`
97			`// wire [PIXEL_DATA_WIDTH-1:0] pixel2_sig;`
98			`// wire [PIXEL_DATA_WIDTH-1:0] pixel3_sig;`
99			`// wire [PIXEL_DATA_WIDTH-1:0] pixel4_sig;`
100
101			`ifndef DEBUG
102			`assign median_word = {pixel1,pixel2,pixel3,pixel4};`
103			`endif
104
105			`// Common network output signals`
106			`wire [PIXEL_DATA_WIDTH-1:0] c3l;`
107			`wire [PIXEL_DATA_WIDTH-1:0] c3h;`
108			`wire [PIXEL_DATA_WIDTH-1:0] c3m;`
109			`wire [PIXEL_DATA_WIDTH-1:0] c3l_reg;`
110			`wire [PIXEL_DATA_WIDTH-1:0] c3h_reg;`
111			`wire [PIXEL_DATA_WIDTH-1:0] c3m_reg;`
112			`wire [PIXEL_DATA_WIDTH-1:0] c2l;`
113			`wire [PIXEL_DATA_WIDTH-1:0] c2h;`
114			`wire [PIXEL_DATA_WIDTH-1:0] c2m;`
115			`wire [PIXEL_DATA_WIDTH-1:0] c2l_reg;`
116			`wire [PIXEL_DATA_WIDTH-1:0] c2h_reg;`
117			`wire [PIXEL_DATA_WIDTH-1:0] c2m_reg;`
118			`wire [PIXEL_DATA_WIDTH-1:0] c1l;`
119			`wire [PIXEL_DATA_WIDTH-1:0] c1h;`
120			`wire [PIXEL_DATA_WIDTH-1:0] c1m;`
121			`wire [PIXEL_DATA_WIDTH-1:0] c0h;`
122			`wire [PIXEL_DATA_WIDTH-1:0] c0m;`
123			`wire [PIXEL_DATA_WIDTH-1:0] c0l;`
124
125			`// Delay signals to be placed over the output registers`
126			`wire [PIXEL_DATA_WIDTH-1:0] p1_sig;`
127			`wire [PIXEL_DATA_WIDTH-1:0] p2_sig;`
128			`wire [PIXEL_DATA_WIDTH-1:0] p3_sig;`
129
130			`//------------------------------------------------------------`
131			`// Windowing Memory Address Controller`
132			`//------------------------------------------------------------`
133			`state_machine`
134			`#(`
135			`.LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),`
136			`.IMG_WIDTH(IMG_WIDTH),`
137			`.IMG_HEIGHT(IMG_HEIGHT)`
138			`) window_contol (`
139			`.clk(clk), // Clock`
140			`.rst_n(rst_n), // Asynchronous reset active low`
141
142			`.raddr_a(raddr_a),`
143			`.raddr_b(raddr_b),`
144			`.raddr_c(raddr_c),`
145
146			`.waddr(waddr)`
147			`);`
148
149			`//------------------------------------------------------------`
150			`// Pixel registers`
151			`//------------------------------------------------------------`
152			`// always @(posedge clk or negedge rst_n)`
153			`// begin : pixel_reg`
154			`// if(~rst_n) begin`
155			`// pixel1 <= {PIXEL_DATA_WIDTH{1'b0}};`
156			`// pixel2 <= {PIXEL_DATA_WIDTH{1'b0}};`
157			`// pixel3 <= {PIXEL_DATA_WIDTH{1'b0}};`
158			`// pixel4 <= {PIXEL_DATA_WIDTH{1'b0}};`
159			`// end else begin`
160			`// pixel1 <= pixel1_sig;`
161			`// pixel2 <= pixel2_sig;`
162			`// pixel3 <= pixel3_sig;`
163			`// //pixel4 <= pixel4_sig;`
164			`// end`
165			`// end`
166
167			`//------------------------------------------------------------`
168			`// Input datapath common network`
169			`//------------------------------------------------------------`
170			`common_network`
171			`#(`
172			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
173			`) common_network_u0 (`
174			`.x2_y1(x2_y1),`
175			`.x2_y0(x2_y0),`
176			`.x2_ym1(x2_ym1),`
177			`.x1_y1(x1_y1),`
178			`.x1_y0(x1_y0),`
179			`.x1_ym1(x1_ym1),`
180			`.x0_y1(x0_y1),`
181			`.x0_y0(x0_y0),`
182			`.x0_ym1(x0_ym1),`
183			`.xm1_y1(xm1_y1),`
184			`.xm1_y0(xm1_y0),`
185			`.xm1_ym1(xm1_ym1),`
186
187			`.c3l(c3l),`
188			`.c3h(c3h),`
189			`.c3m(c3m),`
190			`.c2l(c2l),`
191			`.c2h(c2h),`
192			`.c2m(c2m),`
193			`.c1l(c1l),`
194			`.c1h(c1h),`
195			`.c1m(c1m),`
196			`.c0h(c0h),`
197			`.c0m(c0m),`
198			`.c0l(c0l)`
199			`);`
200
201			`//------------------------------------------------------------`
202			`// Pipeline Registers`
203			`//------------------------------------------------------------`
204			`dff_3_pipe`
205			`#(`
206			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
207			`) dff_c3_pipe (`
208			`.clk(clk),`
209			`.rst_n(rst_n),`
210			`.d0(c3h),`
211			`.d1(c3m),`
212			`.d2(c3l),`
213
214			`.q0(c3h_reg),`
215			`.q1(c3m_reg),`
216			`.q2(c3l_reg)`
217			`);`
218
219			`dff_3_pipe`
220			`#(`
221			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
222			`) dff_c2_pipe (`
223			`.clk(clk),`
224			`.rst_n(rst_n),`
225			`.d0(c2h),`
226			`.d1(c2m),`
227			`.d2(c2l),`
228
229			`.q0(c2h_reg),`
230			`.q1(c2m_reg),`
231			`.q2(c2l_reg)`
232			`);`
233
234			`// Output pieline registers (P1, P2, P3)`
235			`dff_3_pipe`
236			`#(`
237			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
238			`) dff_out_pipe (`
239			`.clk(clk),`
240			`.rst_n(rst_n),`
241			`.d0(p1_sig),`
242			`.d1(p2_sig),`
243			`.d2(p3_sig),`
244
245			`.q0(pixel1),`
246			`.q1(pixel2),`
247			`.q2(pixel3)`
248			`);`
249
250			`//------------------------------------------------------------`
251			`// Median Filter Pixel Network`
252			`//------------------------------------------------------------`
253
254			`// Pixel 1`
255			`pixel_network`
256			`#(`
257			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
258			`) pixel_network_u0 (`
259			`.c3h(c1h),`
260			`.c3m(c1m),`
261			`.c3l(c1l),`
262			`.c2h(c0h),`
263			`.c2m(c0m),`
264			`.c2l(c0l),`
265			`.c1h(c3h_reg),`
266			`.c1m(c3m_reg),`
267			`.c1l(c3l_reg),`
268
269			`.median(p1_sig)`
270			`);`
271
272			`pixel_network`
273			`#(`
274			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
275			`) pixel_network_u1 (`
276			`.c3h(c2h),`
277			`.c3m(c2m),`
278			`.c3l(c2l),`
279			`.c2h(c1h),`
280			`.c2m(c1m),`
281			`.c2l(c1l),`
282			`.c1h(c0h),`
283			`.c1m(c0m),`
284			`.c1l(c0l),`
285
286			`.median(p2_sig)`
287			`);`
288
289			`pixel_network`
290			`#(`
291			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
292			`) pixel_network_u2 (`
293			`.c3h(c3h),`
294			`.c3m(c3m),`
295			`.c3l(c3l),`
296			`.c2h(c2h),`
297			`.c2m(c2m),`
298			`.c2l(c2l),`
299			`.c1h(c1h),`
300			`.c1m(c1m),`
301			`.c1l(c1l),`
302
303			`.median(p3_sig)`
304			`);`
305
306			`pixel_network`
307			`#(`
308			`.DATA_WIDTH(PIXEL_DATA_WIDTH)`
309			`) pixel_network_u3 (`
310			`.c3h(c0h),`
311			`.c3m(c0m),`
312			`.c3l(c0l),`
313			`.c2h(c3h_reg),`
314			`.c2m(c3m_reg),`
315			`.c2l(c3l_reg),`
316			`.c1h(c2h_reg),`
317			`.c1m(c2m_reg),`
318			`.c1l(c2l_reg),`
319
320			`.median(pixel4)`
321			`);`
322
323			`endmodule`