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[/] [fpga-median/] [trunk/] [rtl/] [state_machine.v] - Blame information for rev 6

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// +----------------------------------------------------------------------------
// Universidade Federal da Bahia
//------------------------------------------------------------------------------
// PROJECT: FPGA Median Filter
//------------------------------------------------------------------------------
// FILE NAME            : median.v
// AUTHOR               : Joo Carlos Bittencourt
// AUTHOR'S E-MAIL      : joaocarlos@ieee.org
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION  DATE        AUTHOR        DESCRIPTION
// 1.0      2013-08-13  joao.nunes    initial version
// 2.0      2013-09-06  laur.rami     fix minnor issues on memory address
// -----------------------------------------------------------------------------
// KEYWORDS: median, filter, image processing, state machine
// -----------------------------------------------------------------------------
// PURPOSE: Windowing Memory Address Controller.
// -----------------------------------------------------------------------------
module state_machine
#(
    parameter LUT_ADDR_WIDTH = 10,
    parameter IMG_WIDTH = 234,
    parameter IMG_HEIGHT = 234
)(
    input clk, // Clock
    input rst_n, // Asynchronous reset active low
 
    output reg [LUT_ADDR_WIDTH-1:0] raddr_a,
    output reg [LUT_ADDR_WIDTH-1:0] raddr_b,
    output reg [LUT_ADDR_WIDTH-1:0] raddr_c,
    output reg [LUT_ADDR_WIDTH-1:0] waddr,
    output reg [1:0] window_line_counter,
    output reg [9:0] window_column_counter,
    output reg [9:0] memory_shift
);
 
    reg valid;
 
    always @(posedge clk or negedge rst_n)
    begin : out_memory_counter
        if(~rst_n) begin
            waddr <= {LUT_ADDR_WIDTH{1'b0}};
        end else if(valid) begin
            waddr <= waddr + 1'b1;
        end
    end
 
    always @(posedge clk or negedge rst_n)
    begin : addr_counter
        if(~rst_n) begin
            window_column_counter <= 10'd0;
            window_line_counter <= 2'b00;
            raddr_a <= {LUT_ADDR_WIDTH{1'b0}};
            raddr_b <= {LUT_ADDR_WIDTH{1'b0}};
            raddr_c <= {LUT_ADDR_WIDTH{1'b0}};
        end else begin
            if(window_column_counter != ((IMG_WIDTH/4)-1)) begin
                window_column_counter <= window_column_counter + 1'b1;
                valid <= 1'b1;
                raddr_a <= raddr_a + 1'b1;
                raddr_b <= raddr_b + 1'b1;
                raddr_c <= raddr_c + 1'b1;
            end else begin
                window_column_counter <= 10'd0;
                case (window_line_counter)
                    2'b00 :
                    begin
                        raddr_a <= raddr_a + 1'b1;
                        raddr_b <= raddr_b - window_column_counter;
                        raddr_c <= raddr_c - window_column_counter;
                        window_line_counter = window_line_counter + 1'b1;
                    end
                    2'b01 :
                    begin
                        raddr_b <= raddr_b + 1'b1;
                        raddr_a <= raddr_a - window_column_counter;
                        raddr_c <= raddr_c - window_column_counter;
                        window_line_counter = window_line_counter + 1'b1;
                    end
                    2'b10 :
                    begin
                        raddr_b <= raddr_b - window_column_counter;
                        raddr_a <= raddr_a - window_column_counter;
                        raddr_c <= raddr_c + 1'b1;
                        window_line_counter = 2'b00;
                    end
                    default :
                    begin
                        raddr_a <= {LUT_ADDR_WIDTH{1'b0}};
                        raddr_b <= {LUT_ADDR_WIDTH{1'b0}};
                        raddr_c <= {LUT_ADDR_WIDTH{1'b0}};
                    end
                endcase
            end
        end
    end
 
endmodule

Line No.	Rev	Author	Line
1	2	joaocarlos	`// +----------------------------------------------------------------------------`
2			`// Universidade Federal da Bahia`
3			`//------------------------------------------------------------------------------`
4			`// PROJECT: FPGA Median Filter`
5			`//------------------------------------------------------------------------------`
6			`// FILE NAME : median.v`
7			`// AUTHOR : Joo Carlos Bittencourt`
8			`// AUTHOR'S E-MAIL : joaocarlos@ieee.org`
9			`// -----------------------------------------------------------------------------`
10			`// RELEASE HISTORY`
11			`// VERSION DATE AUTHOR DESCRIPTION`
12			`// 1.0 2013-08-13 joao.nunes initial version`
13			`// 2.0 2013-09-06 laur.rami fix minnor issues on memory address`
14			`// -----------------------------------------------------------------------------`
15			`// KEYWORDS: median, filter, image processing, state machine`
16			`// -----------------------------------------------------------------------------`
17			`// PURPOSE: Windowing Memory Address Controller.`
18			`// -----------------------------------------------------------------------------`
19			`module state_machine`
20			`#(`
21			`parameter LUT_ADDR_WIDTH = 10,`
22			`parameter IMG_WIDTH = 234,`
23			`parameter IMG_HEIGHT = 234`
24			`)(`
25			`input clk, // Clock`
26			`input rst_n, // Asynchronous reset active low`
27
28			`output reg [LUT_ADDR_WIDTH-1:0] raddr_a,`
29			`output reg [LUT_ADDR_WIDTH-1:0] raddr_b,`
30			`output reg [LUT_ADDR_WIDTH-1:0] raddr_c,`
31			`output reg [LUT_ADDR_WIDTH-1:0] waddr,`
32			`output reg [1:0] window_line_counter,`
33			`output reg [9:0] window_column_counter,`
34			`output reg [9:0] memory_shift`
35			`);`
36
37			`reg valid;`
38
39			`always @(posedge clk or negedge rst_n)`
40			`begin : out_memory_counter`
41			`if(~rst_n) begin`
42			`waddr <= {LUT_ADDR_WIDTH{1'b0}};`
43			`end else if(valid) begin`
44			`waddr <= waddr + 1'b1;`
45			`end`
46			`end`
47
48			`always @(posedge clk or negedge rst_n)`
49			`begin : addr_counter`
50			`if(~rst_n) begin`
51			`window_column_counter <= 10'd0;`
52			`window_line_counter <= 2'b00;`
53			`raddr_a <= {LUT_ADDR_WIDTH{1'b0}};`
54			`raddr_b <= {LUT_ADDR_WIDTH{1'b0}};`
55			`raddr_c <= {LUT_ADDR_WIDTH{1'b0}};`
56			`end else begin`
57			`if(window_column_counter != ((IMG_WIDTH/4)-1)) begin`
58			`window_column_counter <= window_column_counter + 1'b1;`
59			`valid <= 1'b1;`
60			`raddr_a <= raddr_a + 1'b1;`
61			`raddr_b <= raddr_b + 1'b1;`
62			`raddr_c <= raddr_c + 1'b1;`
63			`end else begin`
64			`window_column_counter <= 10'd0;`
65			`case (window_line_counter)`
66			`2'b00 :`
67			`begin`
68			`raddr_a <= raddr_a + 1'b1;`
69			`raddr_b <= raddr_b - window_column_counter;`
70			`raddr_c <= raddr_c - window_column_counter;`
71			`window_line_counter = window_line_counter + 1'b1;`
72			`end`
73			`2'b01 :`
74			`begin`
75			`raddr_b <= raddr_b + 1'b1;`
76			`raddr_a <= raddr_a - window_column_counter;`
77			`raddr_c <= raddr_c - window_column_counter;`
78			`window_line_counter = window_line_counter + 1'b1;`
79			`end`
80			`2'b10 :`
81			`begin`
82			`raddr_b <= raddr_b - window_column_counter;`
83			`raddr_a <= raddr_a - window_column_counter;`
84			`raddr_c <= raddr_c + 1'b1;`
85			`window_line_counter = 2'b00;`
86			`end`
87			`default :`
88			`begin`
89			`raddr_a <= {LUT_ADDR_WIDTH{1'b0}};`
90			`raddr_b <= {LUT_ADDR_WIDTH{1'b0}};`
91			`raddr_c <= {LUT_ADDR_WIDTH{1'b0}};`
92			`end`
93			`endcase`
94			`end`
95			`end`
96			`end`
97
98			`endmodule`

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[/] [fpga-median/] [trunk/] [rtl/] [state_machine.v] - Blame information for rev 6