URL https://opencores.org/ocsvn/fpga-median/fpga-median/trunk

Subversion Repositories fpga-median

[/] [fpga-median/] [trunk/] [sim/] [tb/] [dut_if.sv] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	joaocarlos	`// +----------------------------------------------------------------------------`
2			`// Universidade Federal da Bahia`
3			`//------------------------------------------------------------------------------`
4			`// PROJECT: FPGA Median Filter`
5			`//------------------------------------------------------------------------------`
6			`// FILE NAME : dut_if.sv`
7			`// AUTHOR : Laue Rami Souza Costa de Jesus`
8			`// -----------------------------------------------------------------------------`
9
10			`interface dut_if (input bit clk);`
11
12			`//input signals task`
13
14			`logic rst_n;`
15			`logic start;`
16
17			`logic [7:0] pixel1;`
18			`logic [7:0] pixel2;`
19			`logic [7:0] pixel3;`
20			`logic [7:0] pixel4;`
21
22			`logic [31:0] word0;`
23			`logic [31:0] word1;`
24			`logic [31:0] word2;`
25
26			`logic [9:0] waddr;`
27			`logic [1:0] window_line_counter;`
28
29			`//output signals task`
30
31			`logic [31:0] ch_word0;`
32			`logic [31:0] ch_word1;`
33			`logic [31:0] ch_word2;`
34
35			`logic end_of_operation;`
36
37			`logic [7:0] result [0:51983];`
38
39			`endinterface`