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[/] [fpga-median/] [trunk/] [sim/] [tb/] [dut_if.sv] - Blame information for rev 9

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1 9 joaocarlos
/* --------------------------------------------------------------------------------
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 This file is part of FPGA Median Filter.
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    FPGA Median Filter is free software: you can redistribute it and/or modify
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    it under the terms of the GNU General Public License as published by
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    the Free Software Foundation, either version 3 of the License, or
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    (at your option) any later version.
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    FPGA Median Filter is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with FPGA Median Filter.  If not, see .
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-------------------------------------------------------------------------------- */
17 2 joaocarlos
// +----------------------------------------------------------------------------
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// Universidade Federal da Bahia
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//------------------------------------------------------------------------------
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// PROJECT: FPGA Median Filter
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//------------------------------------------------------------------------------
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// FILE NAME            : dut_if.sv
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// AUTHOR               : Laue Rami Souza Costa de Jesus
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// -----------------------------------------------------------------------------
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interface dut_if (input bit clk);
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//input signals task
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logic rst_n;
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logic start;
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logic [7:0] pixel1;
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logic [7:0] pixel2;
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logic [7:0] pixel3;
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logic [7:0] pixel4;
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logic [31:0] word0;
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logic [31:0] word1;
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logic [31:0] word2;
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logic [9:0] waddr;
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logic [1:0] window_line_counter;
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//output signals task
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logic [31:0] ch_word0;
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logic [31:0] ch_word1;
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logic [31:0] ch_word2;
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logic end_of_operation;
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logic [7:0] result [0:51983];
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endinterface

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