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[/] [fpga-median/] [trunk/] [sim/] [tb/] [median_tb_directed.sv] - Blame information for rev 2

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// +----------------------------------------------------------------------------
// Universidade Federal da Bahia
//------------------------------------------------------------------------------
// PROJECT: FPGA Median Filter
//------------------------------------------------------------------------------
// FILE NAME            : median_tb.v
// AUTHOR               : João Carlos Bittencourt
// AUTHOR'S E-MAIL      : joaocarlos@ieee.org
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION  DATE        AUTHOR        DESCRIPTION
// 1.0      2013-08-27  joao.nunes    initial version
// 1.1      2013-09-04  laue.rami     modified version
// -----------------------------------------------------------------------------
// KEYWORDS: median, filter, image processing
// -----------------------------------------------------------------------------
// PURPOSE: Testbench for Median filter.
// -----------------------------------------------------------------------------
`define IMG_HEIGHT 'd320
`define IMG_WIDTH  'd320
module median_tb;
 
    `include "../tb/driver.sv"
 
    driver driver_u0;
 
    localparam PERIOD = 10;
    localparam PIXEL_DATA_WIDTH = 8;
    localparam LUT_ADDR_WIDTH = 14; // Input LUTs
    localparam MEM_ADDR_WIDTH = 14; // Output Memory
 
    bit clk;
 
    wire [MEM_ADDR_WIDTH-1:0] raddr_a;
    wire [MEM_ADDR_WIDTH-1:0] raddr_b;
    wire [MEM_ADDR_WIDTH-1:0] raddr_c;
    wire [MEM_ADDR_WIDTH-1:0] waddr_a;
    wire [MEM_ADDR_WIDTH-1:0] waddr_b;
    wire [MEM_ADDR_WIDTH-1:0] waddr_c;
 
 
    wire [MEM_ADDR_WIDTH-1:0] waddr;
 
    reg [(PIXEL_DATA_WIDTH*4)-1:0] word0;
    reg [(PIXEL_DATA_WIDTH*4)-1:0] word1;
    reg [(PIXEL_DATA_WIDTH*4)-1:0] word2;
 
    wire [31:0] w_data_bram0;
    wire [31:0] w_data_bram1;
    wire [31:0] w_data_bram2;
 
    //dut_if interface
    dut_if dut_if (clk);
 
    //driver
 
    always #(PERIOD/2) clk = ~clk;
 
    dual_port_ram
    #(
      .MEMFILE("./memA.hex"),
      .DATA_WIDTH('d32),
      .ADDR_WIDTH('d14)
    )
    BRAM0
    (
      .clk(clk),
      .r_ena(1'b1),
      .w_ena(1'b0),
      .w_data(w_data_bram0),
      .w_addr(waddr_a),
      .r_addr(raddr_a),
      .r_data(dut_if.word0)
    );
 
    dual_port_ram
    #(
      .MEMFILE("./memB.hex"),
      .DATA_WIDTH('d32),
      .ADDR_WIDTH('d14)
    )
    BRAM1
    (
      .clk(clk),
      .r_ena(1'b1),
      .w_ena(1'b0),
      .w_data(w_data_bram1),
      .w_addr(waddr_b),
      .r_addr(raddr_b),
      .r_data(dut_if.word1)
    );
 
    dual_port_ram
    #(
      .MEMFILE("./memC.hex"),
      .DATA_WIDTH('d32),
      .ADDR_WIDTH('d14)
    )
    BRAM2
    (
      .clk(clk),
      .r_ena(1'b1),
      .w_ena(1'b0),
      .w_data(w_data_bram2),
      .w_addr(waddr_c),
      .r_addr(raddr_c),
      .r_data(dut_if.word2)
    );
 
    median
    #(
        .MEM_DATA_WIDTH(PIXEL_DATA_WIDTH*4),
        .PIXEL_DATA_WIDTH(PIXEL_DATA_WIDTH),
        .LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),
        .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH),
        .IMG_WIDTH(`IMG_WIDTH),
        .IMG_HEIGHT(`IMG_HEIGHT)
    ) dut_u0 (
        .clk(clk), // Clock
        .rst_n(dut_if.rst_n), // Asynchronous reset active low
        .word0(dut_if.ch_word0),
        .word1(dut_if.ch_word1),
        .word2(dut_if.ch_word2),
        .pixel1(dut_if.pixel1),
        .pixel2(dut_if.pixel2),
        .pixel3(dut_if.pixel3),
        .pixel4(dut_if.pixel4),
        .raddr_a(raddr_a),
        .raddr_b(raddr_b),
        .raddr_c(raddr_c),
        .waddr(dut_if.waddr)
    );
 
    always@(*)begin
       dut_if.window_line_counter  = dut_u0.window_contol.window_line_counter;
    end
 
    initial begin
        $display("INICIO -------");
        driver_u0 = new(dut_if);
        driver_u0.init();
        driver_u0.receive_data();
        driver_u0.reorganize_lines();
        wait(dut_if.end_of_operation);
        driver_u0.write_file();
        #(PERIOD*3)
        repeat(100)@(negedge clk);
        $stop;
    end
 
endmodule

Line No.	Rev	Author	Line
1	2	joaocarlos	`// +----------------------------------------------------------------------------`
2			`// Universidade Federal da Bahia`
3			`//------------------------------------------------------------------------------`
4			`// PROJECT: FPGA Median Filter`
5			`//------------------------------------------------------------------------------`
6			`// FILE NAME : median_tb.v`
7			`// AUTHOR : João Carlos Bittencourt`
8			`// AUTHOR'S E-MAIL : joaocarlos@ieee.org`
9			`// -----------------------------------------------------------------------------`
10			`// RELEASE HISTORY`
11			`// VERSION DATE AUTHOR DESCRIPTION`
12			`// 1.0 2013-08-27 joao.nunes initial version`
13			`// 1.1 2013-09-04 laue.rami modified version`
14			`// -----------------------------------------------------------------------------`
15			`// KEYWORDS: median, filter, image processing`
16			`// -----------------------------------------------------------------------------`
17			`// PURPOSE: Testbench for Median filter.`
18			`// -----------------------------------------------------------------------------`
19			`define IMG_HEIGHT 'd320
20			`define IMG_WIDTH 'd320
21			`module median_tb;`
22
23			`include "../tb/driver.sv"
24
25			`driver driver_u0;`
26
27			`localparam PERIOD = 10;`
28			`localparam PIXEL_DATA_WIDTH = 8;`
29			`localparam LUT_ADDR_WIDTH = 14; // Input LUTs`
30			`localparam MEM_ADDR_WIDTH = 14; // Output Memory`
31
32			`bit clk;`
33
34			`wire [MEM_ADDR_WIDTH-1:0] raddr_a;`
35			`wire [MEM_ADDR_WIDTH-1:0] raddr_b;`
36			`wire [MEM_ADDR_WIDTH-1:0] raddr_c;`
37			`wire [MEM_ADDR_WIDTH-1:0] waddr_a;`
38			`wire [MEM_ADDR_WIDTH-1:0] waddr_b;`
39			`wire [MEM_ADDR_WIDTH-1:0] waddr_c;`
40
41
42			`wire [MEM_ADDR_WIDTH-1:0] waddr;`
43
44			`reg [(PIXEL_DATA_WIDTH*4)-1:0] word0;`
45			`reg [(PIXEL_DATA_WIDTH*4)-1:0] word1;`
46			`reg [(PIXEL_DATA_WIDTH*4)-1:0] word2;`
47
48			`wire [31:0] w_data_bram0;`
49			`wire [31:0] w_data_bram1;`
50			`wire [31:0] w_data_bram2;`
51
52			`//dut_if interface`
53			`dut_if dut_if (clk);`
54
55			`//driver`
56
57			`always #(PERIOD/2) clk = ~clk;`
58
59			`dual_port_ram`
60			`#(`
61			`.MEMFILE("./memA.hex"),`
62			`.DATA_WIDTH('d32),`
63			`.ADDR_WIDTH('d14)`
64			`)`
65			`BRAM0`
66			`(`
67			`.clk(clk),`
68			`.r_ena(1'b1),`
69			`.w_ena(1'b0),`
70			`.w_data(w_data_bram0),`
71			`.w_addr(waddr_a),`
72			`.r_addr(raddr_a),`
73			`.r_data(dut_if.word0)`
74			`);`
75
76			`dual_port_ram`
77			`#(`
78			`.MEMFILE("./memB.hex"),`
79			`.DATA_WIDTH('d32),`
80			`.ADDR_WIDTH('d14)`
81			`)`
82			`BRAM1`
83			`(`
84			`.clk(clk),`
85			`.r_ena(1'b1),`
86			`.w_ena(1'b0),`
87			`.w_data(w_data_bram1),`
88			`.w_addr(waddr_b),`
89			`.r_addr(raddr_b),`
90			`.r_data(dut_if.word1)`
91			`);`
92
93			`dual_port_ram`
94			`#(`
95			`.MEMFILE("./memC.hex"),`
96			`.DATA_WIDTH('d32),`
97			`.ADDR_WIDTH('d14)`
98			`)`
99			`BRAM2`
100			`(`
101			`.clk(clk),`
102			`.r_ena(1'b1),`
103			`.w_ena(1'b0),`
104			`.w_data(w_data_bram2),`
105			`.w_addr(waddr_c),`
106			`.r_addr(raddr_c),`
107			`.r_data(dut_if.word2)`
108			`);`
109
110			`median`
111			`#(`
112			`.MEM_DATA_WIDTH(PIXEL_DATA_WIDTH*4),`
113			`.PIXEL_DATA_WIDTH(PIXEL_DATA_WIDTH),`
114			`.LUT_ADDR_WIDTH(LUT_ADDR_WIDTH),`
115			`.MEM_ADDR_WIDTH(MEM_ADDR_WIDTH),`
116			.IMG_WIDTH(`IMG_WIDTH),
117			.IMG_HEIGHT(`IMG_HEIGHT)
118			`) dut_u0 (`
119			`.clk(clk), // Clock`
120			`.rst_n(dut_if.rst_n), // Asynchronous reset active low`
121			`.word0(dut_if.ch_word0),`
122			`.word1(dut_if.ch_word1),`
123			`.word2(dut_if.ch_word2),`
124			`.pixel1(dut_if.pixel1),`
125			`.pixel2(dut_if.pixel2),`
126			`.pixel3(dut_if.pixel3),`
127			`.pixel4(dut_if.pixel4),`
128			`.raddr_a(raddr_a),`
129			`.raddr_b(raddr_b),`
130			`.raddr_c(raddr_c),`
131			`.waddr(dut_if.waddr)`
132			`);`
133
134			`always@(*)begin`
135			`dut_if.window_line_counter = dut_u0.window_contol.window_line_counter;`
136			`end`
137
138			`initial begin`
139			`$display("INICIO -------");`
140			`driver_u0 = new(dut_if);`
141			`driver_u0.init();`
142			`driver_u0.receive_data();`
143			`driver_u0.reorganize_lines();`
144			`wait(dut_if.end_of_operation);`
145			`driver_u0.write_file();`
146			`#(PERIOD*3)`
147			`repeat(100)@(negedge clk);`
148			`$stop;`
149			`end`
150
151			`endmodule`

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[/] [fpga-median/] [trunk/] [sim/] [tb/] [median_tb_directed.sv] - Blame information for rev 2