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[/] [fpu/] [tags/] [third_release/] [fcmp/] [test_bench/] [test_top.v] - Blame information for rev 10

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/////////////////////////////////////////////////////////////////////
////                                                             ////
////  FPU                                                        ////
////  Floating Point Unit (Single precision)                     ////
////                                                             ////
////  TEST BENCH                                                 ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000 Rudolf Usselmann                         ////
////                    rudi@asics.ws                            ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
 
`timescale 1ns / 100ps
 
module test;
 
reg             clk;
reg     [31:0]   opa;
reg     [31:0]   opb;
wire    [3:0]    sum;
wire            inf, snan, qnan;
wire            div_by_zero;
wire            altb, blta, aeqb;
wire            unordered;
 
reg     [3:0]    exp;
reg     [31:0]   opa1;
reg     [31:0]   opb1;
reg     [2:0]    fpu_op;
reg     [3:0]    rmode;
reg             start;
reg     [75:0]   tmem[0:500000];
reg     [75:0]   tmp;
reg     [7:0]    oper;
reg     [7:0]    exc;
integer         i;
wire            ine;
reg             match;
wire            overflow, underflow;
wire            zero;
reg             exc_err;
reg             m0, m1, m2;
reg     [1:0]    fpu_rmode;
reg     [3:0]    test_rmode;
reg     [4:0]    test_sel;
reg             fp_fasu;
reg             fp_mul;
reg             fp_div;
reg             fp_combo;
reg             fp_i2f;
reg             fp_0fcmp;
reg             test_exc;
reg             show_prog;
event           error_event;
 
integer         error, vcount;
 
always #50 clk = ~clk;
 
initial
   begin
        $display ("\n\nFloating Point Compare Version 1.0\n\n");
        clk = 0;
        start = 0;
 
        error = 0;
        vcount = 0;
 
        show_prog = 0;
 
        test_exc = 1;
        test_sel   = 5'b11111;
 
        @(posedge clk);
 
        $display("\n\nTesting FP CMP Unit\n");
 
        if(test_sel[0])
           begin
                $display("\nRunning Pat 0 Test ...\n");
                $readmemh ("../test_vectors/fcmp/fcmp_pat0.hex", tmem);
                run_test;
           end
 
        if(test_sel[1])
           begin
                $display("\nRunning Pat 1 Test ...\n");
                $readmemh ("../test_vectors/fcmp/fcmp_pat1.hex", tmem);
                run_test;
           end
 
        if(test_sel[2])
           begin
                $display("\nRunning Pat 2 Test ...\n");
                $readmemh ("../test_vectors/fcmp/fcmp_pat2.hex", tmem);
                run_test;
           end
 
        if(test_sel[3])
           begin
                $display("\nRunning Random Lg. Num Test ...\n");
                $readmemh ("../test_vectors/fcmp/fcmp_lg.hex", tmem);
                run_test;
           end
 
        if(test_sel[4])
           begin
                $display("\nRunning Random Sm. Num Test ...\n");
                $readmemh ("../test_vectors/fcmp/fcmp_sm.hex", tmem);
                run_test;
           end
 
        repeat (4)      @(posedge clk);
        $display("\n\n");
 
        $display("\n\nAll test Done !\n\n");
        $display("Run %0d vecors, found %0d errors.\n\n",vcount, error);
 
        $finish;
   end
 
 
task run_test;
begin
        @(posedge clk);
        #1;
        opa = 32'h0;
        opb = 32'hx;
 
        @(posedge clk);
        #1;
 
        i=0;
        while( |opa !== 1'bx )
           begin
 
                @(posedge clk);
                #1;
                start = 1;
                tmp   = tmem[i];
 
                exc   = tmp[75:68];
                opa   = tmp[67:36];
                opb   = tmp[35:04];
 
                exp   = exc==0 ? tmp[03:00] : 0;
 
                if(show_prog)   $write("Vector: %d\015",i);
 
                i= i+1;
           end
        start = 0;
 
        @(posedge clk);
        #1;
        opa = 32'hx;
        opb = 32'hx;
        fpu_rmode = 2'hx;
 
        @(posedge clk);
        #1;
 
        for(i=0;i<500000;i=i+1)          // Clear Memory
           tmem[i] = 76'hxxxxxxxxxxxxxxxxx;
 
   end
endtask
 
always @(posedge clk)
   begin
 
        #3;
 
        //      Floating Point Exceptions ( exc4 )
        //      -------------------------
        //      float_flag_invalid   =  1,
        //      float_flag_divbyzero =  4,
        //      float_flag_overflow  =  8,
        //      float_flag_underflow = 16,
        //      float_flag_inexact   = 32
 
        exc_err=0;
 
        if(test_exc)
           begin
 
                if(exc[5])
                   begin
                        exc_err=1;
                        $display("\nERROR: INE Exception: Expected: 0, Got 1\n");
                   end
 
                if(exc[3])
                   begin
                        exc_err=1;
                        $display("\nERROR: Overflow Exception: Expected: 0, Got 1\n");
                   end
 
                if(exc[4])
                   begin
                        exc_err=1;
                        $display("\nERROR: Underflow Exception: Expected: 0, Got 1\n");
                   end
 
                if(zero !== !(|opa[30:0]))
                   begin
                        exc_err=1;
                        $display("\nERROR: Zero Detection Failed. ZERO: %h, Sum: %h\n", zero, opa);
                   end
 
 
                if(inf !== (((opa[30:23] == 8'hff) & ((|opa[22:0]) == 1'b0)) | ((opb[30:23] == 8'hff) & ((|opb[22:0]) == 1'b0))) )
                   begin
                        exc_err=1;
                        $display("\nERROR: INF Detection Failed. INF: %h, Sum: %h\n", inf, sum);
                   end
 
                if(unordered !== ( ( &opa[30:23] & |opa[22:0]) | ( &opb[30:23] & |opb[22:0]) ) )
                   begin
                        exc_err=1;
                        $display("\nERROR: UNORDERED Detection Failed. SNAN: %h, OpA: %h, OpB: %h\n", snan, opa, opb);
                   end
 
           end
 
        m0 = ( (|sum) !== 1'b1) & ( (|sum) !== 1'b0);           // result unknown (ERROR)
        m1 = (exp === sum) ;                                    // results are equal
 
        match = m1;
 
        if( (exc_err | !match | m0) & start )
           begin
                $display("\n%t: ERROR: output mismatch. Expected %h, Got %h (%h)", $time, exp, sum, {opa, opb, exp} );
                $write("opa:\t");       disp_fp(opa);
                $write("opb:\t");       disp_fp(opb);
                $display("EXP:\t%b",exp);
                $display("GOT:\t%b",sum);
                $display("\n");
 
                error = error + 1;
           end
 
        if(start)       vcount = vcount + 1;
 
        if(error > 10)
           begin
                @(posedge clk);
                $display("\n\nFound to many errors, aborting ...\n\n");
                $display("Run %0d vecors, found %0d errors.\n\n",vcount, error);
                $finish;
           end
   end
 
assign sum = {1'b0, altb, blta, aeqb};
 
fcmp u0(opa, opb, unordered, altb, blta, aeqb, inf, zero );
 
task disp_fp;
input [31:0]     fp;
 
reg     [63:0]   x;
reg     [7:0]    exp;
 
   begin
 
        exp = fp[30:23];
        if(exp==8'h7f)  $write("(%h %h ( 00 ) %h) ",fp[31], exp, fp[22:0]);
        else
        if(exp>8'h7f)   $write("(%h %h (+%d ) %h) ",fp[31], exp, exp-8'h7f, fp[22:0]);
        else            $write("(%h %h (-%d ) %h) ",fp[31], exp, 8'h7f-exp, fp[22:0]);
 
 
        x[51:0] = {fp[22:0], 29'h0};
        x[63] = fp[31];
        x[62] = fp[30];
        x[61:59] = {fp[29], fp[29], fp[29]};
        x[58:52] = fp[29:23];
 
        $display("\t%f",$bitstoreal(x));
   end
 
endtask
 
endmodule
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Subversion Repositories fpu

[/] [fpu/] [tags/] [third_release/] [fcmp/] [test_bench/] [test_top.v] - Blame information for rev 10

Line No.	Rev	Author	Line
1	8	rudi	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// FPU ////`
4			`//// Floating Point Unit (Single precision) ////`
5			`//// ////`
6			`//// TEST BENCH ////`
7			`//// ////`
8			`//// Author: Rudolf Usselmann ////`
9			`//// rudi@asics.ws ////`
10			`//// ////`
11			`/////////////////////////////////////////////////////////////////////`
12			`//// ////`
13			`//// Copyright (C) 2000 Rudolf Usselmann ////`
14			`//// rudi@asics.ws ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer.////`
20			`//// ////`
21			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
22			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
23			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
24			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
25			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
26			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
27			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
28			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
29			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
30			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
31			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
32			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
33			`//// POSSIBILITY OF SUCH DAMAGE. ////`
34			`//// ////`
35			`/////////////////////////////////////////////////////////////////////`
36
37
38			`timescale 1ns / 100ps
39
40			`module test;`
41
42			`reg clk;`
43			`reg [31:0] opa;`
44			`reg [31:0] opb;`
45			`wire [3:0] sum;`
46			`wire inf, snan, qnan;`
47			`wire div_by_zero;`
48			`wire altb, blta, aeqb;`
49			`wire unordered;`
50
51			`reg [3:0] exp;`
52			`reg [31:0] opa1;`
53			`reg [31:0] opb1;`
54			`reg [2:0] fpu_op;`
55			`reg [3:0] rmode;`
56			`reg start;`
57			`reg [75:0] tmem[0:500000];`
58			`reg [75:0] tmp;`
59			`reg [7:0] oper;`
60			`reg [7:0] exc;`
61			`integer i;`
62			`wire ine;`
63			`reg match;`
64			`wire overflow, underflow;`
65			`wire zero;`
66			`reg exc_err;`
67			`reg m0, m1, m2;`
68			`reg [1:0] fpu_rmode;`
69			`reg [3:0] test_rmode;`
70			`reg [4:0] test_sel;`
71			`reg fp_fasu;`
72			`reg fp_mul;`
73			`reg fp_div;`
74			`reg fp_combo;`
75			`reg fp_i2f;`
76			`reg fp_0fcmp;`
77			`reg test_exc;`
78			`reg show_prog;`
79			`event error_event;`
80
81			`integer error, vcount;`
82
83			`always #50 clk = ~clk;`
84
85			`initial`
86			`begin`
87			`$display ("\n\nFloating Point Compare Version 1.0\n\n");`
88			`clk = 0;`
89			`start = 0;`
90
91			`error = 0;`
92			`vcount = 0;`
93
94			`show_prog = 0;`
95
96			`test_exc = 1;`
97			`test_sel = 5'b11111;`
98
99			`@(posedge clk);`
100
101			`$display("\n\nTesting FP CMP Unit\n");`
102
103			`if(test_sel[0])`
104			`begin`
105			`$display("\nRunning Pat 0 Test ...\n");`
106			`$readmemh ("../test_vectors/fcmp/fcmp_pat0.hex", tmem);`
107			`run_test;`
108			`end`
109
110			`if(test_sel[1])`
111			`begin`
112			`$display("\nRunning Pat 1 Test ...\n");`
113			`$readmemh ("../test_vectors/fcmp/fcmp_pat1.hex", tmem);`
114			`run_test;`
115			`end`
116
117			`if(test_sel[2])`
118			`begin`
119			`$display("\nRunning Pat 2 Test ...\n");`
120			`$readmemh ("../test_vectors/fcmp/fcmp_pat2.hex", tmem);`
121			`run_test;`
122			`end`
123
124			`if(test_sel[3])`
125			`begin`
126			`$display("\nRunning Random Lg. Num Test ...\n");`
127			`$readmemh ("../test_vectors/fcmp/fcmp_lg.hex", tmem);`
128			`run_test;`
129			`end`
130
131			`if(test_sel[4])`
132			`begin`
133			`$display("\nRunning Random Sm. Num Test ...\n");`
134			`$readmemh ("../test_vectors/fcmp/fcmp_sm.hex", tmem);`
135			`run_test;`
136			`end`
137
138			`repeat (4) @(posedge clk);`
139			`$display("\n\n");`
140
141			`$display("\n\nAll test Done !\n\n");`
142			`$display("Run %0d vecors, found %0d errors.\n\n",vcount, error);`
143
144			`$finish;`
145			`end`
146
147
148			`task run_test;`
149			`begin`
150			`@(posedge clk);`
151			`#1;`
152			`opa = 32'h0;`
153			`opb = 32'hx;`
154
155			`@(posedge clk);`
156			`#1;`
157
158			`i=0;`
159			`while( \|opa !== 1'bx )`
160			`begin`
161
162			`@(posedge clk);`
163			`#1;`
164			`start = 1;`
165			`tmp = tmem[i];`
166
167			`exc = tmp[75:68];`
168			`opa = tmp[67:36];`
169			`opb = tmp[35:04];`
170
171			`exp = exc==0 ? tmp[03:00] : 0;`
172
173			`if(show_prog) $write("Vector: %d\015",i);`
174
175			`i= i+1;`
176			`end`
177			`start = 0;`
178
179			`@(posedge clk);`
180			`#1;`
181			`opa = 32'hx;`
182			`opb = 32'hx;`
183			`fpu_rmode = 2'hx;`
184
185			`@(posedge clk);`
186			`#1;`
187
188			`for(i=0;i<500000;i=i+1) // Clear Memory`
189			`tmem[i] = 76'hxxxxxxxxxxxxxxxxx;`
190
191			`end`
192			`endtask`
193
194			`always @(posedge clk)`
195			`begin`
196
197			`#3;`
198
199			`// Floating Point Exceptions ( exc4 )`
200			`// -------------------------`
201			`// float_flag_invalid = 1,`
202			`// float_flag_divbyzero = 4,`
203			`// float_flag_overflow = 8,`
204			`// float_flag_underflow = 16,`
205			`// float_flag_inexact = 32`
206
207			`exc_err=0;`
208
209			`if(test_exc)`
210			`begin`
211
212			`if(exc[5])`
213			`begin`
214			`exc_err=1;`
215			`$display("\nERROR: INE Exception: Expected: 0, Got 1\n");`
216			`end`
217
218			`if(exc[3])`
219			`begin`
220			`exc_err=1;`
221			`$display("\nERROR: Overflow Exception: Expected: 0, Got 1\n");`
222			`end`
223
224			`if(exc[4])`
225			`begin`
226			`exc_err=1;`
227			`$display("\nERROR: Underflow Exception: Expected: 0, Got 1\n");`
228			`end`
229
230			`if(zero !== !(\|opa[30:0]))`
231			`begin`
232			`exc_err=1;`
233			`$display("\nERROR: Zero Detection Failed. ZERO: %h, Sum: %h\n", zero, opa);`
234			`end`
235
236
237			`if(inf !== (((opa[30:23] == 8'hff) & ((\|opa[22:0]) == 1'b0)) \| ((opb[30:23] == 8'hff) & ((\|opb[22:0]) == 1'b0))) )`
238			`begin`
239			`exc_err=1;`
240			`$display("\nERROR: INF Detection Failed. INF: %h, Sum: %h\n", inf, sum);`
241			`end`
242
243			`if(unordered !== ( ( &opa[30:23] & \|opa[22:0]) \| ( &opb[30:23] & \|opb[22:0]) ) )`
244			`begin`
245			`exc_err=1;`
246			`$display("\nERROR: UNORDERED Detection Failed. SNAN: %h, OpA: %h, OpB: %h\n", snan, opa, opb);`
247			`end`
248
249			`end`
250
251			`m0 = ( (\|sum) !== 1'b1) & ( (\|sum) !== 1'b0); // result unknown (ERROR)`
252			`m1 = (exp === sum) ; // results are equal`
253
254			`match = m1;`
255
256			`if( (exc_err \| !match \| m0) & start )`
257			`begin`
258			`$display("\n%t: ERROR: output mismatch. Expected %h, Got %h (%h)", $time, exp, sum, {opa, opb, exp} );`
259			`$write("opa:\t"); disp_fp(opa);`
260			`$write("opb:\t"); disp_fp(opb);`
261			`$display("EXP:\t%b",exp);`
262			`$display("GOT:\t%b",sum);`
263			`$display("\n");`
264
265			`error = error + 1;`
266			`end`
267
268			`if(start) vcount = vcount + 1;`
269
270			`if(error > 10)`
271			`begin`
272			`@(posedge clk);`
273			`$display("\n\nFound to many errors, aborting ...\n\n");`
274			`$display("Run %0d vecors, found %0d errors.\n\n",vcount, error);`
275			`$finish;`
276			`end`
277			`end`
278
279			`assign sum = {1'b0, altb, blta, aeqb};`
280
281			`fcmp u0(opa, opb, unordered, altb, blta, aeqb, inf, zero );`
282
283			`task disp_fp;`
284			`input [31:0] fp;`
285
286			`reg [63:0] x;`
287			`reg [7:0] exp;`
288
289			`begin`
290
291			`exp = fp[30:23];`
292			`if(exp==8'h7f) $write("(%h %h ( 00 ) %h) ",fp[31], exp, fp[22:0]);`
293			`else`
294			`if(exp>8'h7f) $write("(%h %h (+%d ) %h) ",fp[31], exp, exp-8'h7f, fp[22:0]);`
295			`else $write("(%h %h (-%d ) %h) ",fp[31], exp, 8'h7f-exp, fp[22:0]);`
296
297
298			`x[51:0] = {fp[22:0], 29'h0};`
299			`x[63] = fp[31];`
300			`x[62] = fp[30];`
301			`x[61:59] = {fp[29], fp[29], fp[29]};`
302			`x[58:52] = fp[29:23];`
303
304			`$display("\t%f",$bitstoreal(x));`
305			`end`
306
307			`endtask`
308
309			`endmodule`
310
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