OpenCores
URL https://opencores.org/ocsvn/fpu/fpu/trunk

Subversion Repositories fpu

[/] [fpu/] [trunk/] [verilog/] [primitives.v] - Blame information for rev 11

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 rudi
/////////////////////////////////////////////////////////////////////
2
////                                                             ////
3
////  Primitives                                                 ////
4
////  FPU Primitives                                             ////
5
////                                                             ////
6
////  Author: Rudolf Usselmann                                   ////
7
////          rudi@asics.ws                                      ////
8
////                                                             ////
9
/////////////////////////////////////////////////////////////////////
10
////                                                             ////
11
//// Copyright (C) 2000 Rudolf Usselmann                         ////
12
////                    rudi@asics.ws                            ////
13
////                                                             ////
14
//// This source file may be used and distributed without        ////
15
//// restriction provided that this copyright statement is not   ////
16
//// removed from the file and that any derivative work contains ////
17
//// the original copyright notice and the associated disclaimer.////
18
////                                                             ////
19
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
20
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
21
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
22
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
23
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
24
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
25
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
26
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
27
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
28
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
29
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
30
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
31
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
32
////                                                             ////
33
/////////////////////////////////////////////////////////////////////
34
 
35
 
36
`timescale 1ns / 100ps
37
 
38
 
39
////////////////////////////////////////////////////////////////////////
40
//
41
// Add/Sub
42
//
43
 
44
module add_sub27(add, opa, opb, sum, co);
45
input           add;
46
input   [26:0]   opa, opb;
47
output  [26:0]   sum;
48
output          co;
49
 
50
 
51
 
52
assign {co, sum} = add ? (opa + opb) : (opa - opb);
53
 
54
endmodule
55
 
56
////////////////////////////////////////////////////////////////////////
57
//
58
// Multiply
59
//
60
 
61
module mul_r2(clk, opa, opb, prod);
62
input           clk;
63
input   [23:0]   opa, opb;
64
output  [47:0]   prod;
65
 
66
reg     [47:0]   prod1, prod;
67
 
68
always @(posedge clk)
69
        prod1 <= #1 opa * opb;
70
 
71
always @(posedge clk)
72
        prod <= #1 prod1;
73
 
74
endmodule
75
 
76
////////////////////////////////////////////////////////////////////////
77
//
78
// Divide
79
//
80
 
81
module div_r2(clk, opa, opb, quo, rem);
82
input           clk;
83
input   [49:0]   opa;
84
input   [23:0]   opb;
85
output  [49:0]   quo, rem;
86
 
87
reg     [49:0]   quo, rem, quo1, remainder;
88
 
89
always @(posedge clk)
90
        quo1 <= #1 opa / opb;
91
 
92
always @(posedge clk)
93
        quo <= #1 quo1;
94
 
95
always @(posedge clk)
96
        remainder <= #1 opa % opb;
97
 
98
always @(posedge clk)
99
        rem <= #1 remainder;
100
 
101
endmodule
102
 
103
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.