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jidan |
-------------------------------------------------------------------------------
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--
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-- Project: <Floating Point Unit Core>
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--
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-- Description: top entity
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-------------------------------------------------------------------------------
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--
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-- 100101011010011100100
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-- 110000111011100100000
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-- 100000111011000101101
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-- 100010111100101111001
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-- 110000111011101101001
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-- 010000001011101001010
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-- 110100111001001100001
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-- 110111010000001100111
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-- 110110111110001011101
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-- 101110110010111101000
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-- 100000010111000000000
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--
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-- Author: Jidan Al-eryani
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-- E-mail: jidan@gmx.net
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--
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-- Copyright (C) 2006
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.comppack.all;
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use work.fpupack.all;
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entity fpu is
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port (
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clk_i : in std_logic;
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-- Input Operands A & B
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opa_i : in std_logic_vector(FP_WIDTH-1 downto 0); -- Default: FP_WIDTH=32
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opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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-- fpu operations (fpu_op_i):
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-- ========================
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-- 000 = add,
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-- 001 = substract,
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-- 010 = multiply,
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-- 011 = divide,
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-- 100 = square root
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-- 101 = unused
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-- 110 = unused
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-- 111 = unused
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fpu_op_i : in std_logic_vector(2 downto 0);
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-- Rounding Mode:
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-- ==============
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-- 00 = round to nearest even(default),
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-- 01 = round to zero,
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-- 10 = round up,
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-- 11 = round down
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rmode_i : in std_logic_vector(1 downto 0);
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-- Output port
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output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
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-- Control signals
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start_i : in std_logic; -- is also restart signal
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ready_o : out std_logic;
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-- Exceptions
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ine_o : out std_logic; -- inexact
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overflow_o : out std_logic; -- overflow
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underflow_o : out std_logic; -- underflow
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div_zero_o : out std_logic; -- divide by zero
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inf_o : out std_logic; -- infinity
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zero_o : out std_logic; -- zero
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qnan_o : out std_logic; -- queit Not-a-Number
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snan_o : out std_logic -- signaling Not-a-Number
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);
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end fpu;
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architecture rtl of fpu is
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constant MUL_SERIAL: integer range 0 to 1 := 0; -- 0 for parallel multiplier, 1 for serial
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constant MUL_COUNT: integer:= 10; --10 for parallel multiplier, 33 for serial
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-- Input/output registers
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signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
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signal s_fpu_op_i : std_logic_vector(2 downto 0);
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signal s_rmode_i : std_logic_vector(1 downto 0);
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signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
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signal s_ine_o, s_overflow_o, s_underflow_o, s_div_zero_o, s_inf_o, s_zero_o, s_qnan_o, s_snan_o : std_logic;
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type t_state is (waiting,busy);
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signal s_state : t_state;
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signal s_start_i : std_logic;
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signal s_count : integer;
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signal s_output1 : std_logic_vector(FP_WIDTH-1 downto 0);
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signal s_infa, s_infb : std_logic;
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jidan |
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-- ***Add/Substract units signals***
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signal prenorm_addsub_fracta_28_o, prenorm_addsub_fractb_28_o : std_logic_vector(27 downto 0);
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signal prenorm_addsub_exp_o : std_logic_vector(7 downto 0);
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signal addsub_fract_o : std_logic_vector(27 downto 0);
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signal addsub_sign_o : std_logic;
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signal postnorm_addsub_output_o : std_logic_vector(31 downto 0);
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signal postnorm_addsub_ine_o : std_logic;
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-- ***Multiply units signals***
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signal pre_norm_mul_exp_10 : std_logic_vector(9 downto 0);
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signal pre_norm_mul_fracta_24 : std_logic_vector(23 downto 0);
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signal pre_norm_mul_fractb_24 : std_logic_vector(23 downto 0);
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signal mul_24_fract_48 : std_logic_vector(47 downto 0);
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signal mul_24_sign : std_logic;
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signal serial_mul_fract_48 : std_logic_vector(47 downto 0);
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signal serial_mul_sign : std_logic;
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signal mul_fract_48: std_logic_vector(47 downto 0);
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signal mul_sign: std_logic;
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signal post_norm_mul_output : std_logic_vector(31 downto 0);
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signal post_norm_mul_ine : std_logic;
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-- ***Division units signals***
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signal pre_norm_div_dvdnd : std_logic_vector(49 downto 0);
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signal pre_norm_div_dvsor : std_logic_vector(26 downto 0);
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signal pre_norm_div_exp : std_logic_vector(EXP_WIDTH+1 downto 0);
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signal serial_div_qutnt : std_logic_vector(26 downto 0);
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signal serial_div_rmndr : std_logic_vector(26 downto 0);
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signal serial_div_sign : std_logic;
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signal serial_div_div_zero : std_logic;
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signal post_norm_div_output : std_logic_vector(31 downto 0);
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signal post_norm_div_ine : std_logic;
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-- ***Square units***
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signal pre_norm_sqrt_fracta_o : std_logic_vector(51 downto 0);
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signal pre_norm_sqrt_exp_o : std_logic_vector(7 downto 0);
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signal sqrt_sqr_o : std_logic_vector(25 downto 0);
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signal sqrt_ine_o : std_logic;
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signal post_norm_sqrt_output : std_logic_vector(31 downto 0);
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signal post_norm_sqrt_ine_o : std_logic;
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begin
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--***Add/Substract units***
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i_prenorm_addsub: pre_norm_addsub
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port map (
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clk_i => clk_i,
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opa_i => s_opa_i,
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opb_i => s_opb_i,
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fracta_28_o => prenorm_addsub_fracta_28_o,
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fractb_28_o => prenorm_addsub_fractb_28_o,
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exp_o=> prenorm_addsub_exp_o);
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i_addsub: addsub_28
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port map(
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clk_i => clk_i,
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fpu_op_i => s_fpu_op_i(0),
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fracta_i => prenorm_addsub_fracta_28_o,
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fractb_i => prenorm_addsub_fractb_28_o,
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signa_i => s_opa_i(31),
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signb_i => s_opb_i(31),
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fract_o => addsub_fract_o,
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sign_o => addsub_sign_o);
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i_postnorm_addsub: post_norm_addsub
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port map(
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clk_i => clk_i,
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opa_i => s_opa_i,
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opb_i => s_opb_i,
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fract_28_i => addsub_fract_o,
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exp_i => prenorm_addsub_exp_o,
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sign_i => addsub_sign_o,
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fpu_op_i => s_fpu_op_i(0),
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rmode_i => s_rmode_i,
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output_o => postnorm_addsub_output_o,
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ine_o => postnorm_addsub_ine_o
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);
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--***Multiply units***
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i_pre_norm_mul: pre_norm_mul
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port map(
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clk_i => clk_i,
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opa_i => s_opa_i,
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opb_i => s_opb_i,
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exp_10_o => pre_norm_mul_exp_10,
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fracta_24_o => pre_norm_mul_fracta_24,
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fractb_24_o => pre_norm_mul_fractb_24);
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i_mul_24 : mul_24
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port map(
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clk_i => clk_i,
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fracta_i => pre_norm_mul_fracta_24,
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fractb_i => pre_norm_mul_fractb_24,
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signa_i => s_opa_i(31),
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signb_i => s_opb_i(31),
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start_i => start_i,
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fract_o => mul_24_fract_48,
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sign_o => mul_24_sign,
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ready_o => open);
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i_serial_mul : serial_mul
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port map(
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clk_i => clk_i,
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fracta_i => pre_norm_mul_fracta_24,
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fractb_i => pre_norm_mul_fractb_24,
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signa_i => s_opa_i(31),
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signb_i => s_opb_i(31),
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start_i => s_start_i,
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fract_o => serial_mul_fract_48,
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sign_o => serial_mul_sign,
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ready_o => open);
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-- serial or parallel multiplier will be choosed depending on constant MUL_SERIAL
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mul_fract_48 <= mul_24_fract_48 when MUL_SERIAL=0 else serial_mul_fract_48;
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mul_sign <= mul_24_sign when MUL_SERIAL=0 else serial_mul_sign;
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i_post_norm_mul : post_norm_mul
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port map(
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clk_i => clk_i,
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opa_i => s_opa_i,
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opb_i => s_opb_i,
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exp_10_i => pre_norm_mul_exp_10,
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fract_48_i => mul_fract_48,
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sign_i => mul_24_sign,
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rmode_i => s_rmode_i,
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output_o => post_norm_mul_output,
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ine_o => post_norm_mul_ine
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);
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--***Division units***
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i_pre_norm_div : pre_norm_div
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port map(
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clk_i => clk_i,
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opa_i => s_opa_i,
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opb_i => s_opb_i,
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exp_10_o => pre_norm_div_exp,
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dvdnd_50_o => pre_norm_div_dvdnd,
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dvsor_27_o => pre_norm_div_dvsor);
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i_serial_div : serial_div
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port map(
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clk_i=> clk_i,
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dvdnd_i => pre_norm_div_dvdnd,
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dvsor_i => pre_norm_div_dvsor,
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sign_dvd_i => s_opa_i(31),
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sign_div_i => s_opb_i(31),
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start_i => s_start_i,
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ready_o => open,
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qutnt_o => serial_div_qutnt,
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rmndr_o => serial_div_rmndr,
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sign_o => serial_div_sign,
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div_zero_o => serial_div_div_zero);
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i_post_norm_div : post_norm_div
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port map(
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clk_i => clk_i,
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opa_i => s_opa_i,
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opb_i => s_opb_i,
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qutnt_i => serial_div_qutnt,
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rmndr_i => serial_div_rmndr,
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exp_10_i => pre_norm_div_exp,
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sign_i => serial_div_sign,
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rmode_i => s_rmode_i,
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output_o => post_norm_div_output,
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ine_o => post_norm_div_ine);
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--***Square units***
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i_pre_norm_sqrt : pre_norm_sqrt
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port map(
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clk_i => clk_i,
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opa_i => s_opa_i,
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fracta_52_o => pre_norm_sqrt_fracta_o,
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exp_o => pre_norm_sqrt_exp_o);
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i_sqrt: sqrt
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generic map(RD_WIDTH=>52, SQ_WIDTH=>26)
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port map(
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clk_i => clk_i,
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rad_i => pre_norm_sqrt_fracta_o,
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start_i => s_start_i,
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ready_o => open,
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sqr_o => sqrt_sqr_o,
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ine_o => sqrt_ine_o);
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i_post_norm_sqrt : post_norm_sqrt
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port map(
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clk_i => clk_i,
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opa_i => s_opa_i,
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fract_26_i => sqrt_sqr_o,
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exp_i => pre_norm_sqrt_exp_o,
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ine_i => sqrt_ine_o,
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rmode_i => s_rmode_i,
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output_o => post_norm_sqrt_output,
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ine_o => post_norm_sqrt_ine_o);
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334 |
|
|
|
335 |
|
|
|
336 |
|
|
|
337 |
|
|
-----------------------------------------------------------------
|
338 |
|
|
|
339 |
|
|
-- Input Register
|
340 |
|
|
process(clk_i)
|
341 |
|
|
begin
|
342 |
|
|
if rising_edge(clk_i) then
|
343 |
|
|
s_opa_i <= opa_i;
|
344 |
|
|
s_opb_i <= opb_i;
|
345 |
|
|
s_fpu_op_i <= fpu_op_i;
|
346 |
|
|
s_rmode_i <= rmode_i;
|
347 |
|
|
s_start_i <= start_i;
|
348 |
|
|
end if;
|
349 |
|
|
end process;
|
350 |
|
|
|
351 |
|
|
-- Output Register
|
352 |
|
|
process(clk_i)
|
353 |
|
|
begin
|
354 |
|
|
if rising_edge(clk_i) then
|
355 |
|
|
output_o <= s_output_o;
|
356 |
|
|
ine_o <= s_ine_o;
|
357 |
|
|
overflow_o <= s_overflow_o;
|
358 |
|
|
underflow_o <= s_underflow_o;
|
359 |
|
|
div_zero_o <= s_div_zero_o;
|
360 |
|
|
inf_o <= s_inf_o;
|
361 |
|
|
zero_o <= s_zero_o;
|
362 |
|
|
qnan_o <= s_qnan_o;
|
363 |
|
|
snan_o <= s_snan_o;
|
364 |
|
|
end if;
|
365 |
|
|
end process;
|
366 |
|
|
|
367 |
|
|
|
368 |
|
|
-- FSM
|
369 |
|
|
process(clk_i)
|
370 |
|
|
begin
|
371 |
|
|
if rising_edge(clk_i) then
|
372 |
|
|
if s_start_i ='1' then
|
373 |
|
|
s_state <= busy;
|
374 |
|
|
s_count <= 0;
|
375 |
|
|
elsif s_count=5 and ((fpu_op_i="000") or (fpu_op_i="001")) then
|
376 |
|
|
s_state <= waiting;
|
377 |
|
|
ready_o <= '1';
|
378 |
|
|
s_count <=0;
|
379 |
|
|
elsif s_count=MUL_COUNT and fpu_op_i="010" then
|
380 |
|
|
s_state <= waiting;
|
381 |
|
|
ready_o <= '1';
|
382 |
|
|
s_count <=0;
|
383 |
6 |
jidan |
elsif s_count=33 and fpu_op_i="011" then
|
384 |
2 |
jidan |
s_state <= waiting;
|
385 |
|
|
ready_o <= '1';
|
386 |
|
|
s_count <=0;
|
387 |
|
|
elsif s_count=33 and fpu_op_i="100" then
|
388 |
|
|
s_state <= waiting;
|
389 |
|
|
ready_o <= '1';
|
390 |
|
|
s_count <=0;
|
391 |
|
|
elsif s_state=busy then
|
392 |
|
|
s_count <= s_count + 1;
|
393 |
|
|
else
|
394 |
|
|
s_state <= waiting;
|
395 |
|
|
ready_o <= '0';
|
396 |
|
|
end if;
|
397 |
|
|
end if;
|
398 |
|
|
end process;
|
399 |
|
|
|
400 |
|
|
-- Output Multiplexer
|
401 |
|
|
process(clk_i)
|
402 |
|
|
begin
|
403 |
|
|
if rising_edge(clk_i) then
|
404 |
|
|
if fpu_op_i="000" or fpu_op_i="001" then
|
405 |
6 |
jidan |
s_output1 <= postnorm_addsub_output_o;
|
406 |
2 |
jidan |
s_ine_o <= postnorm_addsub_ine_o;
|
407 |
|
|
elsif fpu_op_i="010" then
|
408 |
6 |
jidan |
s_output1 <= post_norm_mul_output;
|
409 |
2 |
jidan |
s_ine_o <= post_norm_mul_ine;
|
410 |
|
|
elsif fpu_op_i="011" then
|
411 |
6 |
jidan |
s_output1 <= post_norm_div_output;
|
412 |
2 |
jidan |
s_ine_o <= post_norm_div_ine;
|
413 |
|
|
elsif fpu_op_i="100" then
|
414 |
6 |
jidan |
s_output1 <= post_norm_sqrt_output;
|
415 |
2 |
jidan |
s_ine_o <= post_norm_sqrt_ine_o;
|
416 |
|
|
else
|
417 |
6 |
jidan |
s_output1 <= (others => '0');
|
418 |
2 |
jidan |
s_ine_o <= '0';
|
419 |
|
|
end if;
|
420 |
|
|
end if;
|
421 |
|
|
end process;
|
422 |
|
|
|
423 |
6 |
jidan |
|
424 |
|
|
s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0';
|
425 |
|
|
s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0';
|
426 |
|
|
|
427 |
|
|
|
428 |
|
|
--In round down: the subtraction of two equal numbers other than zero are always -0!!!
|
429 |
|
|
process(s_output1, s_rmode_i, s_div_zero_o, s_infa, s_infb, s_qnan_o, s_snan_o, s_zero_o, s_fpu_op_i, s_opa_i, s_opb_i )
|
430 |
|
|
begin
|
431 |
|
|
if s_rmode_i="00" or (s_div_zero_o or (s_infa or s_infb) or s_qnan_o or s_snan_o)='1' then --round-to-nearest-even
|
432 |
|
|
s_output_o <= s_output1;
|
433 |
|
|
elsif s_rmode_i="01" and s_output1(30 downto 23)="11111111" then
|
434 |
|
|
--In round-to-zero: the sum of two non-infinity operands is never infinity,even if an overflow occures
|
435 |
|
|
s_output_o <= s_output1(31) & "1111111011111111111111111111111";
|
436 |
|
|
elsif s_rmode_i="10" and s_output1(31 downto 23)="111111111" then
|
437 |
|
|
--In round-up: the sum of two non-infinity operands is never negative infinity,even if an overflow occures
|
438 |
|
|
s_output_o <= "11111111011111111111111111111111";
|
439 |
|
|
elsif s_rmode_i="11" then
|
440 |
|
|
--In round-down: a-a= -0
|
441 |
|
|
if (s_fpu_op_i="000" or s_fpu_op_i="001") and s_zero_o='1' and (s_opa_i(31) or (s_fpu_op_i(0) xor s_opb_i(31)))='1' then
|
442 |
|
|
s_output_o <= "1" & s_output1(30 downto 0);
|
443 |
|
|
--In round-down: the sum of two non-infinity operands is never postive infinity,even if an overflow occures
|
444 |
|
|
elsif s_output1(31 downto 23)="011111111" then
|
445 |
|
|
s_output_o <= "01111111011111111111111111111111";
|
446 |
|
|
else
|
447 |
|
|
s_output_o <= s_output1;
|
448 |
|
|
end if;
|
449 |
|
|
else
|
450 |
|
|
s_output_o <= s_output1;
|
451 |
|
|
end if;
|
452 |
|
|
end process;
|
453 |
|
|
|
454 |
|
|
|
455 |
2 |
jidan |
-- Generate Exceptions
|
456 |
6 |
jidan |
s_underflow_o <= '1' when s_output1(30 downto 23)="00000000" and s_ine_o='1' else '0';
|
457 |
|
|
s_overflow_o <= '1' when s_output1(30 downto 23)="11111111" and s_ine_o='1' else '0';
|
458 |
2 |
jidan |
s_div_zero_o <= serial_div_div_zero when fpu_op_i="011" else '0';
|
459 |
6 |
jidan |
s_inf_o <= '1' when s_output1(30 downto 23)="11111111" and (s_qnan_o or s_snan_o)='0' else '0';
|
460 |
|
|
s_zero_o <= '1' when or_reduce(s_output1(30 downto 0))='0' else '0';
|
461 |
|
|
s_qnan_o <= '1' when s_output1(30 downto 0)=QNAN else '0';
|
462 |
2 |
jidan |
s_snan_o <= '1' when s_opa_i(30 downto 0)=SNAN or s_opb_i(30 downto 0)=SNAN else '0';
|
463 |
|
|
|
464 |
|
|
|
465 |
|
|
end rtl;
|