Subversion Repositories fpu100

-------------------------------------------------------------------------------

--

-- Project:     <Floating Point Unit Core>

--      

-- Description: FPU package wich contains constants and functions needed in the FPU core

-------------------------------------------------------------------------------

--

--                              100101011010011100100

--                              110000111011100100000

--                              100000111011000101101

--                              100010111100101111001

--                              110000111011101101001

--                              010000001011101001010

--                              110100111001001100001

--                              110111010000001100111

--                              110110111110001011101

--                              101110110010111101000

--                              100000010111000000000

--

--      Author:          Jidan Al-eryani 

--      E-mail:          jidan@gmx.net

--

--  Copyright (C) 2006

--

--      This source file may be used and distributed without        

--      restriction provided that this copyright statement is not   

--      removed from the file and that any derivative work contains 

--      the original copyright notice and the associated disclaimer.

--                                                           

--              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     

--      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   

--      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   

--      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      

--      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         

--      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    

--      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   

--      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        

--      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  

--      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  

--      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  

--      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         

--      POSSIBILITY OF SUCH DAMAGE. 

--

library  ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

package fpupack is

        -- Data width of floating-point number. Deafult: 32

        constant FP_WIDTH : integer := 32;

        -- Data width of fraction. Deafult: 23

        constant FRAC_WIDTH : integer := 23;

        -- Data width of exponent. Deafult: 8

        constant EXP_WIDTH : integer := 8;

        -- Infinty FP format

        constant INF  : std_logic_vector(30 downto 0) := "1111111100000000000000000000000";

        -- QNaN (Quit Not a Number) FP format (without sign bit)

    constant QNAN : std_logic_vector(30 downto 0) := "1111111110000000000000000000001";

    -- SNaN (Signaling Not a Number) FP format (without sign bit)

    constant SNAN : std_logic_vector(30 downto 0) := "1111111100000000000000000000001";

    -- count the  zeros starting from left

    function count_l_zeros (signal s_vector: std_logic_vector) return std_logic_vector;

    -- count the zeros starting from right

        function count_r_zeros (signal s_vector: std_logic_vector) return std_logic_vector;

end fpupack;

package body fpupack is

    -- count the  zeros starting from left

        function count_l_zeros (signal s_vector: std_logic_vector) return std_logic_vector is

                variable v_count : std_logic_vector(5 downto 0);

        begin

                v_count := "000000";

                for i in s_vector'range loop

                        case s_vector(i) is

                                when '0' => v_count := v_count + "000001";

                                when others => exit;

                        end case;

                end loop;

                return v_count;

        end count_l_zeros;

        -- count the zeros starting from right

        function count_r_zeros (signal s_vector: std_logic_vector) return std_logic_vector is

                variable v_count : std_logic_vector(5 downto 0);

        begin

                v_count := "000000";

                for i in 0 to s_vector'length-1 loop

                        case s_vector(i) is

                                when '0' => v_count := v_count + "000001";

                                when others => exit;

                        end case;

                end loop;

                return v_count;

        end count_r_zeros;

end fpupack;