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Subversion Repositories fpu100

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set REL= .\test_bench
 
vlib work
 
vcom fpupack.vhd
vcom pre_norm_addsub.vhd
vcom addsub_28.vhd
vcom post_norm_addsub.vhd
vcom pre_norm_mul.vhd
vcom mul_24.vhd
vcom serial_mul.vhd
vcom post_norm_mul.vhd
vcom pre_norm_div.vhd
vcom serial_div.vhd
vcom post_norm_div.vhd
vcom pre_norm_sqrt.vhd
vcom sqrt.vhd
vcom post_norm_sqrt.vhd
vcom comppack.vhd
vcom fpu.vhd
 
rem *** compile FPU II . Only for simulation!
vcom %REL%\FPU_II\*.*
 
vcom %REL%\tb_fpu.vhd
 
 
 
pause Start simulation?
 
 
vsim -do fpu_wave.do tb_fpu
 
 

Line No.	Rev	Author	Line
1	2	jidan	`set REL= .\test_bench`
2
3			`vlib work`
4
5			`vcom fpupack.vhd`
6			`vcom pre_norm_addsub.vhd`
7			`vcom addsub_28.vhd`
8			`vcom post_norm_addsub.vhd`
9			`vcom pre_norm_mul.vhd`
10			`vcom mul_24.vhd`
11			`vcom serial_mul.vhd`
12			`vcom post_norm_mul.vhd`
13			`vcom pre_norm_div.vhd`
14			`vcom serial_div.vhd`
15			`vcom post_norm_div.vhd`
16			`vcom pre_norm_sqrt.vhd`
17			`vcom sqrt.vhd`
18			`vcom post_norm_sqrt.vhd`
19			`vcom comppack.vhd`
20			`vcom fpu.vhd`
21
22			`rem *** compile FPU II . Only for simulation!`
23			`vcom %REL%\FPU_II\.`
24
25			`vcom %REL%\tb_fpu.vhd`
26
27
28
29			`pause Start simulation?`
30
31
32			`vsim -do fpu_wave.do tb_fpu`
33
34

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Subversion Repositories fpu100

[/] [fpu100/] [branches/] [avendor/] [fpusim.bat] - Blame information for rev 28