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jidan |
-------------------------------------------------------------------------------
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--
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-- Project: <Floating Point Unit Core>
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--
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-- Description: post-normalization entity for the addition/subtraction unit
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-------------------------------------------------------------------------------
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--
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-- 100101011010011100100
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-- 110000111011100100000
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-- 100000111011000101101
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-- 100010111100101111001
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-- 110000111011101101001
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-- 010000001011101001010
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-- 110100111001001100001
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-- 110111010000001100111
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-- 110110111110001011101
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-- 101110110010111101000
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-- 100000010111000000000
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--
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-- Author: Jidan Al-eryani
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-- E-mail: jidan@gmx.net
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--
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-- Copyright (C) 2006
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.fpupack.all;
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entity post_norm_addsub is
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port(
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clk_i : in std_logic;
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opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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fract_28_i : in std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
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exp_i : in std_logic_vector(EXP_WIDTH-1 downto 0);
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sign_i : in std_logic;
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fpu_op_i : in std_logic;
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rmode_i : in std_logic_vector(1 downto 0);
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output_o : out std_logic_vector(FP_WIDTH-1 downto 0);
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ine_o : out std_logic
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);
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end post_norm_addsub;
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architecture rtl of post_norm_addsub is
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signal s_opa_i, s_opb_i : std_logic_vector(FP_WIDTH-1 downto 0);
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signal s_fract_28_i : std_logic_vector(FRAC_WIDTH+4 downto 0);
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signal s_exp_i : std_logic_vector(EXP_WIDTH-1 downto 0);
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signal s_sign_i : std_logic;
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signal s_fpu_op_i : std_logic;
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signal s_rmode_i : std_logic_vector(1 downto 0);
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signal s_output_o : std_logic_vector(FP_WIDTH-1 downto 0);
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signal s_ine_o : std_logic;
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signal s_overflow : std_logic;
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signal s_shr1, s_shr2, s_shl : std_logic;
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signal s_expr1_9, s_expr2_9, s_expl_9 : std_logic_vector(EXP_WIDTH downto 0);
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signal s_exp_shr1, s_exp_shr2, s_exp_shl : std_logic_vector(EXP_WIDTH-1 downto 0);
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signal s_fract_shr1, s_fract_shr2, s_fract_shl : std_logic_vector(FRAC_WIDTH+4 downto 0);
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signal s_zeros : std_logic_vector(5 downto 0);
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signal shl_pos: std_logic_vector(5 downto 0);
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signal s_fract_1, s_fract_2 : std_logic_vector(FRAC_WIDTH+4 downto 0);
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signal s_exp_1, s_exp_2 : std_logic_vector(EXP_WIDTH-1 downto 0);
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signal s_fract_rnd : std_logic_vector(FRAC_WIDTH+4 downto 0);
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signal s_roundup : std_logic;
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signal s_sticky : std_logic;
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signal s_zero_fract : std_logic;
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signal s_lost : std_logic;
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signal s_infa, s_infb : std_logic;
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signal s_nan_in, s_nan_op, s_nan_a, s_nan_b, s_nan_sign : std_logic;
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begin
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-- Input Register
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--process(clk_i)
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--begin
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-- if rising_edge(clk_i) then
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s_opa_i <= opa_i;
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s_opb_i <= opb_i;
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s_fract_28_i <= fract_28_i;
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s_exp_i <= exp_i;
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s_sign_i <= sign_i;
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s_fpu_op_i <= fpu_op_i;
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s_rmode_i <= rmode_i;
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-- end if;
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--end process;
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-- Output Register
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--process(clk_i)
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--begin
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-- if rising_edge(clk_i) then
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output_o <= s_output_o;
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ine_o <= s_ine_o;
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-- end if;
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--end process;
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-- check if shifting is needed
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s_shr1 <= s_fract_28_i(27);
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s_shl <= '1' when s_fract_28_i(27 downto 26)="00" and s_exp_i /= "00000000" else '0';
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-- stage 1a: right-shift (when necessary)
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s_expr1_9 <= "0"&s_exp_i + "000000001";
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s_fract_shr1 <= shr(s_fract_28_i, "1");
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s_exp_shr1 <= s_expr1_9(7 downto 0);
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-- stage 1b: left-shift (when necessary)
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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-- count the leading zero's of fraction, needed for left-shift
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s_zeros <= count_l_zeros(s_fract_28_i(26 downto 0));
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end if;
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end process;
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s_expl_9 <= ("0"&s_exp_i) - ("000"&s_zeros);
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shl_pos <= "000000" when s_exp_i="00000001" else s_zeros;
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s_fract_shl <= shl(s_fract_28_i, shl_pos);
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s_exp_shl <= "00000000" when s_exp_i="00000001" else s_exp_i - ("00"&shl_pos);
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if s_shr1='1' then
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s_fract_1 <= s_fract_shr1;
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elsif s_shl='1' then
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s_fract_1 <= s_fract_shl;
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else
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s_fract_1 <= s_fract_28_i;
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end if;
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end if;
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end process;
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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if s_shr1='1' then
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s_exp_1 <= s_exp_shr1;
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elsif s_shl='1' then
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s_exp_1 <= s_exp_shl;
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else
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s_exp_1 <= s_exp_i;
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end if;
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end if;
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end process;
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-- round
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s_sticky <='1' when s_fract_1(0)='1' or (s_fract_28_i(0) and s_fract_28_i(27))='1' else '0'; --check last bit, before and after right-shift
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s_roundup <= s_fract_1(2) and ((s_fract_1(1) or s_sticky)or s_fract_1(3)) when s_rmode_i="00" else -- round to nearset even
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(s_fract_1(2) or s_fract_1(1) or s_sticky) and (not s_sign_i) when s_rmode_i="10" else -- round up
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(s_fract_1(2) or s_fract_1(1) or s_sticky) and (s_sign_i) when s_rmode_i="11" else -- round down
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'0'; -- round to zero(truncate = no rounding)
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s_fract_rnd <= s_fract_1 + "0000000000000000000000001000" when s_roundup='1' else s_fract_1;
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-- stage 2: right-shift after rounding (when necessary)
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s_shr2 <= s_fract_rnd(27);
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s_expr2_9 <= ("0"&s_exp_1) + "000000001";
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s_fract_shr2 <= shr(s_fract_rnd, "1");
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s_exp_shr2 <= s_expr2_9(7 downto 0);
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s_fract_2 <= s_fract_shr2 when s_shr2='1' else s_fract_rnd;
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s_exp_2 <= s_exp_shr2 when s_shr2='1' else s_exp_1;
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-------------
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s_infa <= '1' when s_opa_i(30 downto 23)="11111111" else '0';
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s_infb <= '1' when s_opb_i(30 downto 23)="11111111" else '0';
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s_nan_a <= '1' when (s_infa='1' and or_reduce (s_opa_i(22 downto 0))='1') else '0';
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s_nan_b <= '1' when (s_infb='1' and or_reduce (s_opb_i(22 downto 0))='1') else '0';
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s_nan_in <= '1' when s_nan_a='1' or s_nan_b='1' else '0';
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s_nan_op <= '1' when (s_infa and s_infb)='1' and (s_opa_i(31) xor (s_fpu_op_i xor s_opb_i(31)) )='1' else '0'; -- inf-inf=Nan
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s_nan_sign <= s_sign_i when (s_nan_a and s_nan_b)='1' else
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s_opa_i(31) when s_nan_a='1' else
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s_opb_i(31);
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-- check if result is inexact;
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s_lost <= or_reduce(s_fract_28_i(2 downto 0)) or or_reduce(s_fract_1(2 downto 0)) or or_reduce(s_fract_2(2 downto 0));
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s_ine_o <= '1' when (s_lost or s_overflow)='1' and (s_infa or s_infb)='0' else '0';
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s_overflow <='1' when (s_expr1_9(8) or s_expr2_9(8))='1' and (s_infa or s_infb)='0' else '0';
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s_zero_fract <= '1' when s_zeros=27 and s_fract_28_i(27)='0' else '0'; -- '1' if fraction result is zero
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process(s_sign_i, s_exp_2, s_fract_2, s_nan_in, s_nan_op, s_nan_sign, s_infa, s_infb, s_overflow, s_zero_fract)
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begin
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if (s_nan_in or s_nan_op)='1' then
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s_output_o <= s_nan_sign & QNAN;
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elsif (s_infa or s_infb)='1' or s_overflow='1' then
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s_output_o <= s_sign_i & INF;
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elsif s_zero_fract='1' then
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s_output_o <= s_sign_i & ZERO_VECTOR;
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else
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s_output_o <= s_sign_i & s_exp_2 & s_fract_2(25 downto 3);
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end if;
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end process;
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end rtl;
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