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jidan |
-------------------------------------------------------------------------------
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--
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-- Project: <Floating Point Unit Core>
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--
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-- Description: pre-normalization entity for the addition/subtraction unit
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-------------------------------------------------------------------------------
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--
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-- 100101011010011100100
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-- 110000111011100100000
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-- 100000111011000101101
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-- 100010111100101111001
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-- 110000111011101101001
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-- 010000001011101001010
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-- 110100111001001100001
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-- 110111010000001100111
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-- 110110111110001011101
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-- 101110110010111101000
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-- 100000010111000000000
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--
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-- Author: Jidan Al-eryani
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-- E-mail: jidan@gmx.net
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--
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-- Copyright (C) 2006
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--
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-- This source file may be used and distributed without
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-- restriction provided that this copyright statement is not
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-- removed from the file and that any derivative work contains
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-- the original copyright notice and the associated disclaimer.
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--
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-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
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-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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library ieee ;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_misc.all;
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library work;
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use work.fpupack.all;
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entity pre_norm_addsub is
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port(
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clk_i : in std_logic;
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opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);
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fracta_28_o : out std_logic_vector(FRAC_WIDTH+4 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
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fractb_28_o : out std_logic_vector(FRAC_WIDTH+4 downto 0);
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exp_o : out std_logic_vector(EXP_WIDTH-1 downto 0)
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);
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end pre_norm_addsub;
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architecture rtl of pre_norm_addsub is
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signal s_exp_o : std_logic_vector(EXP_WIDTH-1 downto 0);
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signal s_fracta_28_o, s_fractb_28_o : std_logic_vector(FRAC_WIDTH+4 downto 0);
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signal s_expa, s_expb : std_logic_vector(EXP_WIDTH-1 downto 0);
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signal s_fracta, s_fractb : std_logic_vector(FRAC_WIDTH-1 downto 0);
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signal s_fracta_28, s_fractb_28, s_fract_sm_28, s_fract_shr_28 : std_logic_vector(FRAC_WIDTH+4 downto 0);
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signal s_exp_diff : std_logic_vector(EXP_WIDTH-1 downto 0);
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signal s_rzeros : std_logic_vector(5 downto 0);
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signal s_expa_eq_expb : std_logic;
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signal s_expa_lt_expb : std_logic;
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signal s_fracta_1 : std_logic;
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signal s_fractb_1 : std_logic;
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signal s_op_dn,s_opa_dn, s_opb_dn : std_logic;
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signal s_mux_diff : std_logic_vector(1 downto 0);
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signal s_mux_exp : std_logic;
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signal s_sticky : std_logic;
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begin
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-- Input Register
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--process(clk_i)
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--begin
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-- if rising_edge(clk_i) then
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s_expa <= opa_i(30 downto 23);
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s_expb <= opb_i(30 downto 23);
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s_fracta <= opa_i(22 downto 0);
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s_fractb <= opb_i(22 downto 0);
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-- end if;
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--end process;
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-- Output Register
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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exp_o <= s_exp_o;
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fracta_28_o <= s_fracta_28_o;
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fractb_28_o <= s_fractb_28_o;
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end if;
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end process;
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s_expa_eq_expb <= '1' when s_expa = s_expb else '0';
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s_expa_lt_expb <= '1' when s_expa > s_expb else '0';
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-- '1' if fraction is not zero
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s_fracta_1 <= or_reduce(s_fracta);
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s_fractb_1 <= or_reduce(s_fractb);
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-- opa or Opb is denormalized
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s_op_dn <= s_opa_dn or s_opb_dn;
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s_opa_dn <= not or_reduce(s_expa);
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s_opb_dn <= not or_reduce(s_expb);
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-- output the larger exponent
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s_mux_exp <= s_expa_lt_expb;
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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case s_mux_exp is
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when '0' => s_exp_o <= s_expb;
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when '1' => s_exp_o <= s_expa;
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when others => s_exp_o <= "11111111";
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end case;
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end if;
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end process;
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-- convert to an easy to handle floating-point format
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s_fracta_28 <= "01" & s_fracta & "000" when s_opa_dn='0' else "00" & s_fracta & "000";
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s_fractb_28 <= "01" & s_fractb & "000" when s_opb_dn='0' else "00" & s_fractb & "000";
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s_mux_diff <= s_expa_lt_expb & (s_opa_dn xor s_opb_dn);
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process(clk_i)
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begin
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if rising_edge(clk_i) then
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-- calculate howmany postions the fraction will be shifted
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case s_mux_diff is
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when "00"=> s_exp_diff <= s_expb - s_expa;
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when "01"=> s_exp_diff <= s_expb - (s_expa+"00000001");
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when "10"=> s_exp_diff <= s_expa - s_expb;
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when "11"=> s_exp_diff <= s_expa - (s_expb+"00000001");
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when others => s_exp_diff <= "11110000";
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end case;
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end if;
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end process;
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s_fract_sm_28 <= s_fracta_28 when s_expa_lt_expb='0' else s_fractb_28;
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-- shift-right the fraction if necessary
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s_fract_shr_28 <= shr(s_fract_sm_28, s_exp_diff);
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-- count the zeros from right to check if result is inexact
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s_rzeros <= count_r_zeros(s_fract_sm_28);
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s_sticky <= '1' when s_exp_diff > s_rzeros and or_reduce(s_fract_sm_28)='1' else '0';
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s_fracta_28_o <= s_fracta_28 when s_expa_lt_expb='1' else s_fract_shr_28(27 downto 1) & (s_sticky or s_fract_shr_28(0));
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s_fractb_28_o <= s_fractb_28 when s_expa_lt_expb='0' else s_fract_shr_28(27 downto 1) & (s_sticky or s_fract_shr_28(0));
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end rtl;
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