URL https://opencores.org/ocsvn/fpu100/fpu100/trunk

Subversion Repositories fpu100

[/] [fpu100/] [branches/] [avendor/] [test_bench/] [fpusim.bat] - Blame information for rev 21

Details | Compare with Previous | View Log


set REL= ..\
 
vlib work
 
vcom %REL%fpupack.vhd
vcom %REL%pre_norm_addsub.vhd
vcom %REL%addsub_28.vhd
vcom %REL%post_norm_addsub.vhd
vcom %REL%pre_norm_mul.vhd
vcom %REL%mul_24.vhd
vcom %REL%serial_mul.vhd
vcom %REL%post_norm_mul.vhd
vcom %REL%pre_norm_div.vhd
vcom %REL%serial_div.vhd
vcom %REL%post_norm_div.vhd
vcom %REL%pre_norm_sqrt.vhd
vcom %REL%sqrt.vhd
vcom %REL%post_norm_sqrt.vhd
vcom %REL%comppack.vhd
vcom %REL%fpu.vhd
 
vlog FPU_II\*.v
 
vcom txt_util.vhd
vcom tb_fpu.vhd
 
pause Start simulation?
 
vsim -do fpu_wave.do tb_fpu
 
 

Line No.	Rev	Author	Line
1	6	jidan	`set REL= ..\`
2
3			`vlib work`
4
5			`vcom %REL%fpupack.vhd`
6			`vcom %REL%pre_norm_addsub.vhd`
7			`vcom %REL%addsub_28.vhd`
8			`vcom %REL%post_norm_addsub.vhd`
9			`vcom %REL%pre_norm_mul.vhd`
10			`vcom %REL%mul_24.vhd`
11			`vcom %REL%serial_mul.vhd`
12			`vcom %REL%post_norm_mul.vhd`
13			`vcom %REL%pre_norm_div.vhd`
14			`vcom %REL%serial_div.vhd`
15			`vcom %REL%post_norm_div.vhd`
16			`vcom %REL%pre_norm_sqrt.vhd`
17			`vcom %REL%sqrt.vhd`
18			`vcom %REL%post_norm_sqrt.vhd`
19			`vcom %REL%comppack.vhd`
20			`vcom %REL%fpu.vhd`
21
22			`vlog FPU_II\*.v`
23
24			`vcom txt_util.vhd`
25			`vcom tb_fpu.vhd`
26
27			`pause Start simulation?`
28
29			`vsim -do fpu_wave.do tb_fpu`
30
31

Browse

Tools

Subversion Repositories fpu100

[/] [fpu100/] [branches/] [avendor/] [test_bench/] [fpusim.bat] - Blame information for rev 21