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[/] [fpu100/] [trunk/] [comppack.vhd] - Blame information for rev 21

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-------------------------------------------------------------------------------
--
-- Project:     <Floating Point Unit Core>
--      
-- Description: component package
-------------------------------------------------------------------------------
--
--                              100101011010011100100
--                              110000111011100100000
--                              100000111011000101101
--                              100010111100101111001
--                              110000111011101101001
--                              010000001011101001010
--                              110100111001001100001
--                              110111010000001100111
--                              110110111110001011101
--                              101110110010111101000
--                              100000010111000000000
--
--      Author:          Jidan Al-eryani 
--      E-mail:          jidan@gmx.net
--
--  Copyright (C) 2006
--
--      This source file may be used and distributed without        
--      restriction provided that this copyright statement is not   
--      removed from the file and that any derivative work contains 
--      the original copyright notice and the associated disclaimer.
--                                                           
--              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     
--      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   
--      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   
--      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      
--      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         
--      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    
--      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   
--      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        
--      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  
--      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  
--      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  
--      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         
--      POSSIBILITY OF SUCH DAMAGE. 
--
 
library  ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library work;
use work.fpupack.all;
 
package comppack is
 
 
--- Component Declartions ---   
 
        --***Add/Substract units***
 
        component pre_norm_addsub is
        port(clk_i                      : in std_logic;
                         opa_i                  : in std_logic_vector(31 downto 0);
                         opb_i                  : in std_logic_vector(31 downto 0);
                         fracta_28_o            : out std_logic_vector(27 downto 0);     -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
                         fractb_28_o            : out std_logic_vector(27 downto 0);
                         exp_o                  : out std_logic_vector(7 downto 0));
        end component;
 
        component addsub_28 is
        port(clk_i                        : in std_logic;
                         fpu_op_i                  : in std_logic;
                         fracta_i                       : in std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
                         fractb_i                       : in std_logic_vector(27 downto 0);
                         signa_i                        : in std_logic;
                         signb_i                        : in std_logic;
                         fract_o                        : out std_logic_vector(27 downto 0);
                         sign_o                         : out std_logic);
        end component;
 
        component post_norm_addsub is
        port(clk_i                              : in std_logic;
                         opa_i                          : in std_logic_vector(31 downto 0);
                         opb_i                          : in std_logic_vector(31 downto 0);
                         fract_28_i             : in std_logic_vector(27 downto 0);      -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)
                         exp_i                    : in std_logic_vector(7 downto 0);
                         sign_i                   : in std_logic;
                         fpu_op_i                       : in std_logic;
                         rmode_i                        : in std_logic_vector(1 downto 0);
                         output_o                       : out std_logic_vector(31 downto 0);
                         ine_o                          : out std_logic
                );
        end component;
 
        --***Multiplication units***
 
        component pre_norm_mul is
        port(
                         clk_i            : in std_logic;
                         opa_i                  : in std_logic_vector(31 downto 0);
                         opb_i                  : in std_logic_vector(31 downto 0);
                         exp_10_o                       : out std_logic_vector(9 downto 0);
                         fracta_24_o            : out std_logic_vector(23 downto 0);     -- hidden(1) & fraction(23)
                         fractb_24_o            : out std_logic_vector(23 downto 0)
                );
        end component;
 
        component mul_24 is
        port(
                         clk_i                    : in std_logic;
                         fracta_i                       : in std_logic_vector(23 downto 0); -- hidden(1) & fraction(23)
                         fractb_i                       : in std_logic_vector(23 downto 0);
                         signa_i                        : in std_logic;
                         signb_i                        : in std_logic;
                         start_i                        : in std_logic;
                         fract_o                        : out std_logic_vector(47 downto 0);
                         sign_o                         : out std_logic;
                         ready_o                        : out std_logic
                         );
        end component;
 
        component serial_mul is
        port(
                         clk_i                          : in std_logic;
                         fracta_i                       : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
                         fractb_i                       : in std_logic_vector(FRAC_WIDTH downto 0);
                         signa_i                        : in std_logic;
                         signb_i                        : in std_logic;
                         start_i                        : in std_logic;
                         fract_o                        : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
                         sign_o                         : out std_logic;
                         ready_o                        : out std_logic
                         );
        end component;
 
        component post_norm_mul is
        port(
                         clk_i                          : in std_logic;
                         opa_i                                  : in std_logic_vector(31 downto 0);
                         opb_i                                  : in std_logic_vector(31 downto 0);
                         exp_10_i                       : in std_logic_vector(9 downto 0);
                         fract_48_i             : in std_logic_vector(47 downto 0);      -- hidden(1) & fraction(23)
                         sign_i                                 : in std_logic;
                         rmode_i                        : in std_logic_vector(1 downto 0);
                         output_o                               : out std_logic_vector(31 downto 0);
                         ine_o                                  : out std_logic
                );
        end component;
 
        --***Division units***
 
        component pre_norm_div is
        port(
                         clk_i                  : in std_logic;
                         opa_i                  : in std_logic_vector(FP_WIDTH-1 downto 0);
                         opb_i                  : in std_logic_vector(FP_WIDTH-1 downto 0);
                         exp_10_o               : out std_logic_vector(EXP_WIDTH+1 downto 0);
                         dvdnd_50_o             : out std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0);
                         dvsor_27_o             : out std_logic_vector(FRAC_WIDTH+3 downto 0)
                );
        end component;
 
        component serial_div is
        port(
                         clk_i                          : in std_logic;
                         dvdnd_i                        : in std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0); -- hidden(1) & fraction(23)
                         dvsor_i                        : in std_logic_vector(FRAC_WIDTH+3 downto 0);
                         sign_dvd_i             : in std_logic;
                         sign_div_i             : in std_logic;
                         start_i                        : in std_logic;
                         ready_o                        : out std_logic;
                         qutnt_o                        : out std_logic_vector(FRAC_WIDTH+3 downto 0);
                         rmndr_o                        : out std_logic_vector(FRAC_WIDTH+3 downto 0);
                         sign_o                         : out std_logic;
                         div_zero_o                     : out std_logic
                         );
        end component;
 
        component post_norm_div is
        port(
                         clk_i                          : in std_logic;
                         opa_i                          : in std_logic_vector(FP_WIDTH-1 downto 0);
                         opb_i                          : in std_logic_vector(FP_WIDTH-1 downto 0);
                         qutnt_i                        : in std_logic_vector(FRAC_WIDTH+3 downto 0);
                         rmndr_i                        : in std_logic_vector(FRAC_WIDTH+3 downto 0);
                         exp_10_i                       : in std_logic_vector(EXP_WIDTH+1 downto 0);
                         sign_i                         : in std_logic;
                         rmode_i                        : in std_logic_vector(1 downto 0);
                         output_o                       : out std_logic_vector(FP_WIDTH-1 downto 0);
                         ine_o                          : out std_logic
                );
        end component;
 
 
        --***Square units***
 
        component pre_norm_sqrt is
                port(
                         clk_i            : in std_logic;
                         opa_i                  : in std_logic_vector(31 downto 0);
                         fracta_52_o            : out std_logic_vector(51 downto 0);
                         exp_o                          : out std_logic_vector(7 downto 0));
        end component;
 
        component sqrt is
                generic (RD_WIDTH: integer; SQ_WIDTH: integer); -- SQ_WIDTH = RD_WIDTH/2 (+ 1 if odd)
                port(
                         clk_i                   : in std_logic;
                         rad_i                  : in std_logic_vector(RD_WIDTH-1 downto 0); -- hidden(1) & fraction(23)
                         start_i                        : in std_logic;
                         ready_o                        : out std_logic;
                         sqr_o                  : out std_logic_vector(SQ_WIDTH-1 downto 0);
                         ine_o                  : out std_logic);
        end component;
 
 
        component post_norm_sqrt is
        port(    clk_i                          : in std_logic;
                         opa_i                                  : in std_logic_vector(31 downto 0);
                         fract_26_i             : in std_logic_vector(25 downto 0);      -- hidden(1) & fraction(11)
                         exp_i                          : in std_logic_vector(7 downto 0);
                         ine_i                          : in std_logic;
                         rmode_i                        : in std_logic_vector(1 downto 0);
                         output_o                               : out std_logic_vector(31 downto 0);
                         ine_o                                  : out std_logic);
        end component;
 
 
end comppack;

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Subversion Repositories fpu100

[/] [fpu100/] [trunk/] [comppack.vhd] - Blame information for rev 21

Line No.	Rev	Author	Line
1	2	jidan	`-------------------------------------------------------------------------------`
2			`--`
3			`-- Project: <Floating Point Unit Core>`
4			`--`
5			`-- Description: component package`
6			`-------------------------------------------------------------------------------`
7			`--`
8			`-- 100101011010011100100`
9			`-- 110000111011100100000`
10			`-- 100000111011000101101`
11			`-- 100010111100101111001`
12			`-- 110000111011101101001`
13			`-- 010000001011101001010`
14			`-- 110100111001001100001`
15			`-- 110111010000001100111`
16			`-- 110110111110001011101`
17			`-- 101110110010111101000`
18			`-- 100000010111000000000`
19			`--`
20			`-- Author: Jidan Al-eryani`
21			`-- E-mail: jidan@gmx.net`
22			`--`
23			`-- Copyright (C) 2006`
24			`--`
25			`-- This source file may be used and distributed without`
26			`-- restriction provided that this copyright statement is not`
27			`-- removed from the file and that any derivative work contains`
28			`-- the original copyright notice and the associated disclaimer.`
29			`--`
30			-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
31			`-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED`
32			`-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS`
33			`-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR`
34			`-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,`
35			`-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES`
36			`-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE`
37			`-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR`
38			`-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF`
39			`-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
40			`-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT`
41			`-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE`
42			`-- POSSIBILITY OF SUCH DAMAGE.`
43			`--`
44
45			`library ieee;`
46			`use ieee.std_logic_1164.all;`
47			`use ieee.std_logic_unsigned.all;`
48
49			`library work;`
50			`use work.fpupack.all;`
51
52			`package comppack is`
53
54
55			`--- Component Declartions ---`
56
57			`--*Add/Substract units*`
58
59			`component pre_norm_addsub is`
60			`port(clk_i : in std_logic;`
61			`opa_i : in std_logic_vector(31 downto 0);`
62			`opb_i : in std_logic_vector(31 downto 0);`
63			`fracta_28_o : out std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)`
64			`fractb_28_o : out std_logic_vector(27 downto 0);`
65			`exp_o : out std_logic_vector(7 downto 0));`
66			`end component;`
67
68			`component addsub_28 is`
69			`port(clk_i : in std_logic;`
70			`fpu_op_i : in std_logic;`
71			`fracta_i : in std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)`
72			`fractb_i : in std_logic_vector(27 downto 0);`
73			`signa_i : in std_logic;`
74			`signb_i : in std_logic;`
75			`fract_o : out std_logic_vector(27 downto 0);`
76			`sign_o : out std_logic);`
77			`end component;`
78
79			`component post_norm_addsub is`
80			`port(clk_i : in std_logic;`
81			`opa_i : in std_logic_vector(31 downto 0);`
82			`opb_i : in std_logic_vector(31 downto 0);`
83			`fract_28_i : in std_logic_vector(27 downto 0); -- carry(1) & hidden(1) & fraction(23) & guard(1) & round(1) & sticky(1)`
84			`exp_i : in std_logic_vector(7 downto 0);`
85			`sign_i : in std_logic;`
86			`fpu_op_i : in std_logic;`
87			`rmode_i : in std_logic_vector(1 downto 0);`
88			`output_o : out std_logic_vector(31 downto 0);`
89			`ine_o : out std_logic`
90			`);`
91			`end component;`
92
93			`--*Multiplication units*`
94
95			`component pre_norm_mul is`
96			`port(`
97			`clk_i : in std_logic;`
98			`opa_i : in std_logic_vector(31 downto 0);`
99			`opb_i : in std_logic_vector(31 downto 0);`
100			`exp_10_o : out std_logic_vector(9 downto 0);`
101			`fracta_24_o : out std_logic_vector(23 downto 0); -- hidden(1) & fraction(23)`
102			`fractb_24_o : out std_logic_vector(23 downto 0)`
103			`);`
104			`end component;`
105
106			`component mul_24 is`
107			`port(`
108			`clk_i : in std_logic;`
109			`fracta_i : in std_logic_vector(23 downto 0); -- hidden(1) & fraction(23)`
110			`fractb_i : in std_logic_vector(23 downto 0);`
111			`signa_i : in std_logic;`
112			`signb_i : in std_logic;`
113			`start_i : in std_logic;`
114			`fract_o : out std_logic_vector(47 downto 0);`
115			`sign_o : out std_logic;`
116			`ready_o : out std_logic`
117			`);`
118			`end component;`
119
120			`component serial_mul is`
121			`port(`
122			`clk_i : in std_logic;`
123			`fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)`
124			`fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);`
125			`signa_i : in std_logic;`
126			`signb_i : in std_logic;`
127			`start_i : in std_logic;`
128			`fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);`
129			`sign_o : out std_logic;`
130			`ready_o : out std_logic`
131			`);`
132			`end component;`
133
134			`component post_norm_mul is`
135			`port(`
136			`clk_i : in std_logic;`
137			`opa_i : in std_logic_vector(31 downto 0);`
138			`opb_i : in std_logic_vector(31 downto 0);`
139			`exp_10_i : in std_logic_vector(9 downto 0);`
140			`fract_48_i : in std_logic_vector(47 downto 0); -- hidden(1) & fraction(23)`
141			`sign_i : in std_logic;`
142			`rmode_i : in std_logic_vector(1 downto 0);`
143			`output_o : out std_logic_vector(31 downto 0);`
144			`ine_o : out std_logic`
145			`);`
146			`end component;`
147
148			`--*Division units*`
149
150			`component pre_norm_div is`
151			`port(`
152			`clk_i : in std_logic;`
153			`opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);`
154			`opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);`
155			`exp_10_o : out std_logic_vector(EXP_WIDTH+1 downto 0);`
156			`dvdnd_50_o : out std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0);`
157			`dvsor_27_o : out std_logic_vector(FRAC_WIDTH+3 downto 0)`
158			`);`
159			`end component;`
160
161			`component serial_div is`
162			`port(`
163			`clk_i : in std_logic;`
164			`dvdnd_i : in std_logic_vector(2*(FRAC_WIDTH+2)-1 downto 0); -- hidden(1) & fraction(23)`
165			`dvsor_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);`
166			`sign_dvd_i : in std_logic;`
167			`sign_div_i : in std_logic;`
168			`start_i : in std_logic;`
169			`ready_o : out std_logic;`
170			`qutnt_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);`
171			`rmndr_o : out std_logic_vector(FRAC_WIDTH+3 downto 0);`
172			`sign_o : out std_logic;`
173			`div_zero_o : out std_logic`
174			`);`
175			`end component;`
176
177			`component post_norm_div is`
178			`port(`
179			`clk_i : in std_logic;`
180			`opa_i : in std_logic_vector(FP_WIDTH-1 downto 0);`
181			`opb_i : in std_logic_vector(FP_WIDTH-1 downto 0);`
182			`qutnt_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);`
183			`rmndr_i : in std_logic_vector(FRAC_WIDTH+3 downto 0);`
184			`exp_10_i : in std_logic_vector(EXP_WIDTH+1 downto 0);`
185			`sign_i : in std_logic;`
186			`rmode_i : in std_logic_vector(1 downto 0);`
187			`output_o : out std_logic_vector(FP_WIDTH-1 downto 0);`
188			`ine_o : out std_logic`
189			`);`
190			`end component;`
191
192
193			`--*Square units*`
194
195			`component pre_norm_sqrt is`
196			`port(`
197			`clk_i : in std_logic;`
198			`opa_i : in std_logic_vector(31 downto 0);`
199			`fracta_52_o : out std_logic_vector(51 downto 0);`
200			`exp_o : out std_logic_vector(7 downto 0));`
201			`end component;`
202
203			`component sqrt is`
204			`generic (RD_WIDTH: integer; SQ_WIDTH: integer); -- SQ_WIDTH = RD_WIDTH/2 (+ 1 if odd)`
205			`port(`
206			`clk_i : in std_logic;`
207			`rad_i : in std_logic_vector(RD_WIDTH-1 downto 0); -- hidden(1) & fraction(23)`
208			`start_i : in std_logic;`
209			`ready_o : out std_logic;`
210			`sqr_o : out std_logic_vector(SQ_WIDTH-1 downto 0);`
211			`ine_o : out std_logic);`
212			`end component;`
213
214
215			`component post_norm_sqrt is`
216			`port( clk_i : in std_logic;`
217			`opa_i : in std_logic_vector(31 downto 0);`
218			`fract_26_i : in std_logic_vector(25 downto 0); -- hidden(1) & fraction(11)`
219			`exp_i : in std_logic_vector(7 downto 0);`
220			`ine_i : in std_logic;`
221			`rmode_i : in std_logic_vector(1 downto 0);`
222			`output_o : out std_logic_vector(31 downto 0);`
223			`ine_o : out std_logic);`
224			`end component;`
225
226
227			`end comppack;`