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Subversion Repositories fpu_double

[/] [fpu_double/] [tags/] [arelease/] [fpu_mul.vhd] - Blame information for rev 5

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---------------------------------------------------------------------
----                                                             ----
----  FPU                                                        ----
----  Floating Point Unit (Double precision)                     ----
----                                                             ----
----  Author: David Lundgren                                     ----
----          davidklun@gmail.com                                ----
----                                                             ----
---------------------------------------------------------------------
----                                                             ----
---- Copyright (C) 2009 David Lundgren                           ----
----                  davidklun@gmail.com                        ----
----                                                             ----
---- This source file may be used and distributed without        ----
---- restriction provided that this copyright statement is not   ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer.----
----                                                             ----
----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
---- POSSIBILITY OF SUCH DAMAGE.                                 ----
----                                                             ----
---------------------------------------------------------------------
 
        LIBRARY ieee;
        USE ieee.std_logic_1164.all;
        USE ieee.std_logic_arith.all;
        use ieee.std_logic_unsigned.all;
        use ieee.std_logic_misc.all;
        library work;
        use work.fpupack.all;
 
        ENTITY fpu_mul IS
 
   PORT(
      clk : IN     std_logic;
      rst : IN     std_logic;
      enable  : IN     std_logic;
      opa : IN     std_logic_vector (63 DOWNTO 0);
      opb : IN     std_logic_vector (63 DOWNTO 0);
      sign : OUT    std_logic;
      product_7 : OUT    std_logic_vector (55 DOWNTO 0);
      exponent_5 : OUT    std_logic_vector (11 DOWNTO 0)
   );
 
        END fpu_mul;
 
 
        architecture rtl of fpu_mul is
 
        signal          product_shift : std_logic_vector(5 downto 0);
        signal          product_shift_2 : std_logic_vector(5 downto 0);
        signal          mantissa_a : std_logic_vector(51 downto 0);
        signal          mantissa_b : std_logic_vector(51 downto 0);
        signal          exponent_a : std_logic_vector(11 downto 0);
        signal          exponent_b : std_logic_vector(11 downto 0);
        signal          a_is_norm : std_logic;
        signal          b_is_norm : std_logic;
        signal          a_is_zero : std_logic;
        signal          b_is_zero : std_logic;
        signal          in_zero : std_logic;
        signal          exponent_terms : std_logic_vector(11 downto 0);
        signal          exponent_gt_expoffset : std_logic;
        signal          exponent_under : std_logic_vector(11 downto 0);
        signal          exponent_1 : std_logic_vector(11 downto 0);
        signal          exponent : std_logic_vector(11 downto 0);
        signal          exponent_2 : std_logic_vector(11 downto 0);
        signal          exponent_gt_prodshift : std_logic;
        signal          exponent_3 : std_logic_vector(11 downto 0);
        signal          exponent_4 : std_logic_vector(11 downto 0);
        signal          exponent_et_zero : std_logic;
        signal          mul_a : std_logic_vector(52 downto 0);
        signal          mul_b : std_logic_vector(52 downto 0);
        signal          product_a : std_logic_vector(40 downto 0);
        signal          product_b : std_logic_vector(40 downto 0);
        signal          product_c : std_logic_vector(40 downto 0);
        signal          product_d : std_logic_vector(25 downto 0);
        signal          product_e : std_logic_vector(33 downto 0);
        signal          product_f : std_logic_vector(33 downto 0);
        signal          product_g : std_logic_vector(35 downto 0);
        signal          product_h : std_logic_vector(28 downto 0);
        signal          product_i : std_logic_vector(28 downto 0);
        signal          product_j : std_logic_vector(30 downto 0);
        signal          sum_0 : std_logic_vector(41 downto 0);
        signal          sum_1 : std_logic_vector(35 downto 0);
        signal          sum_2 : std_logic_vector(41 downto 0);
        signal          sum_3 : std_logic_vector(35 downto 0);
        signal          sum_4 : std_logic_vector(36 downto 0);
        signal          sum_5 : std_logic_vector(27 downto 0);
        signal          sum_6 : std_logic_vector(29 downto 0);
        signal          sum_7 : std_logic_vector(36 downto 0);
        signal          sum_8 : std_logic_vector(30 downto 0);
        signal          product : std_logic_vector(105 downto 0);
        signal          product_1 : std_logic_vector(105 downto 0);
        signal          product_2 : std_logic_vector(105 downto 0);
        signal          product_3 : std_logic_vector(105 downto 0);
        signal          product_4 : std_logic_vector(105 downto 0);
        signal          product_5 : std_logic_vector(105 downto 0);
        signal          product_6 : std_logic_vector(105 downto 0);
        signal          product_lsb : std_logic;
 
        begin
                product_7 <= '0' & product_6(105 downto 52) & product_lsb;
                exponent <= "000000000000";
        process
        begin
        wait until clk'event and clk = '1';
                if (rst = '1') then
                        sign <= '0';
                        mantissa_a <= (others =>'0');
                        mantissa_b <= (others =>'0');
                        exponent_a <= (others =>'0');
                        exponent_b <= (others =>'0');
                        a_is_norm <= '0';
                        b_is_norm <= '0';
                        a_is_zero <= '0';
                        b_is_zero <= '0';
                        in_zero <= '0';
                        exponent_terms <= (others =>'0');
                        exponent_gt_expoffset <= '0';
                        exponent_under <= (others =>'0');
                        exponent_1 <= (others =>'0');
                        exponent_2 <= (others =>'0');
                        exponent_gt_prodshift <= '0';
                        exponent_3 <= (others =>'0');
                        exponent_4 <= (others =>'0');
                        exponent_et_zero <= '0';
                        mul_a <= (others =>'0');
                        mul_b <= (others =>'0');
                        product_a <= (others =>'0');
                        product_b <= (others =>'0');
                        product_c <= (others =>'0');
                        product_d <= (others =>'0');
                        product_e <= (others =>'0');
                        product_f <= (others =>'0');
                        product_g <= (others =>'0');
                        product_h <= (others =>'0');
                        product_i <= (others =>'0');
                        product_j <= (others =>'0');
                        sum_0 <= (others =>'0');
                        sum_1 <= (others =>'0');
                        sum_2 <= (others =>'0');
                        sum_3 <= (others =>'0');
                        sum_4 <= (others =>'0');
                        sum_5 <= (others =>'0');
                        sum_6 <= (others =>'0');
                        sum_7 <= (others =>'0');
                        sum_8 <= (others =>'0');
                        product <= (others =>'0');
                        product_1 <= (others =>'0');
                        product_2 <= (others =>'0');
                        product_3 <= (others =>'0');
                        product_4 <= (others =>'0');
                        product_5 <= (others =>'0');
                        product_6 <= (others =>'0');
                        product_lsb <= '0';
                        exponent_5 <= (others =>'0');
                        product_shift <= (others =>'0');
                        product_shift_2 <= (others =>'0');
                elsif (enable = '1') then
                        sign <= opa(63) xor opb(63);
                        exponent_a <= '0' & opa(62 downto 52);
                        exponent_b <= '0' & opb(62 downto 52);
                        mantissa_a <= opa(51 downto 0);
                        mantissa_b <= opb(51 downto 0);
                        a_is_norm <= or_reduce(exponent_a);
                        b_is_norm <= or_reduce(exponent_b);
                        a_is_zero <= not or_reduce(opa(62 downto 0));
                        b_is_zero <= not or_reduce(opb(62 downto 0));
                        in_zero <= a_is_zero or b_is_zero;
                        exponent_terms <= exponent_a + exponent_b + ( "0000000000" & not a_is_norm) +
                                                        ("0000000000" & not b_is_norm);
                        if (exponent_terms > "001111111101") then
                                exponent_gt_expoffset <= '1';
                        else
                                exponent_gt_expoffset <= '0';
                        end if;
                        exponent_under <= "001111111110" - exponent_terms;
                        exponent_1 <= exponent_terms - "001111111110";
                        if (exponent_gt_expoffset = '1') then
                                exponent_2 <= exponent_1;
                        else
                                exponent_2 <= exponent;
                        end if;
                        if (exponent_2 > product_shift_2) then
                                exponent_gt_prodshift <= '1';
                        else
                                exponent_gt_prodshift <= '0';
                        end if;
                        exponent_3 <= exponent_2 - product_shift_2;
                        if (exponent_gt_prodshift = '1') then
                                exponent_4 <= exponent_3;
                        else
                                exponent_4 <= exponent;
                        end if;
                        if (exponent_4 = "000000000000") then
                                exponent_et_zero <= '1';
                        else
                                exponent_et_zero <= '0';
                        end if;
                        mul_a <= a_is_norm & mantissa_a;
                        mul_b <= b_is_norm & mantissa_b;
                        product_a <= mul_a(23 downto 0) * mul_b(16 downto 0);
                        product_b <= mul_a(23 downto 0) * mul_b(33 downto 17);
                        product_c <= mul_a(23 downto 0) * mul_b(50 downto 34);
                        product_d <= mul_a(23 downto 0) * mul_b(52 downto 51);
                        product_e <= mul_a(40 downto 24) * mul_b(16 downto 0);
                        product_f <= mul_a(40 downto 24) * mul_b(33 downto 17);
                        product_g <= mul_a(40 downto 24) * mul_b(52 downto 34);
                        product_h <= mul_a(52 downto 41) * mul_b(16 downto 0);
                        product_i <= mul_a(52 downto 41) * mul_b(33 downto 17);
                        product_j <= mul_a(52 downto 41) * mul_b(52 downto 34);
                        sum_0 <= product_a(40 downto 17) + ( '0' & product_b);
                        sum_1 <= ('0' & sum_0(41 downto 7)) + product_e;
                        sum_2 <= sum_1(35 downto 10) + ('0' & product_c);
                        sum_3 <= ( '0' & sum_2(41 downto 7)) + product_h;
                        sum_4 <= ( '0' & sum_3) + product_f;
                        sum_5 <= ('0' & sum_4(36 downto 10)) + product_d;
                        sum_6 <= sum_5(27 downto 7) + ('0' & product_i);
                        sum_7 <= sum_6 + ('0' & product_g);
                        sum_8 <= sum_7(36 downto 17) + product_j;
                        product <=  sum_8 & sum_7(16 downto 0) & sum_5(6 downto 0) & sum_4(9 downto 0) & sum_2(6 downto 0) &
                                                sum_1(9 downto 0) & sum_0(6 downto 0) & product_a(16 downto 0);
                        product_1 <= shr(product, exponent_under);
                        if (exponent_gt_prodshift = '1') then
                                product_5 <= product_3;
                        else
                                product_5 <= product_4;
                        end if;
                        if (exponent_gt_expoffset = '1') then
                                product_2 <= product;
                        else
                                product_2 <= product_1;
                        end if;
                        product_3 <= shl(product_2, product_shift_2);
                        product_4 <= shl(product_2, exponent_2);
                        if (exponent_gt_prodshift = '1') then
                                product_5 <= product_3;
                        else
                                product_5 <= product_4;
                        end if;
                        if (exponent_et_zero = '1') then
                                product_6 <= shr(product_5, conv_std_logic_vector('1', 106));
                        else
                                product_6 <= product_5;
                        end if;
                        product_lsb <= or_reduce(product_6(51 downto 0));
                        if (in_zero = '1') then
                                exponent_5 <= "000000000000";
                        else
                                exponent_5 <= exponent_4;
                        end if;
                        product_shift <= count_zeros_mul(product(105 downto 0));
                        product_shift_2 <= product_shift;
                end if;
        end process;
        end rtl;

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Subversion Repositories fpu_double

[/] [fpu_double/] [tags/] [arelease/] [fpu_mul.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	2	davidklun	`---------------------------------------------------------------------`
2			`---- ----`
3			`---- FPU ----`
4			`---- Floating Point Unit (Double precision) ----`
5			`---- ----`
6			`---- Author: David Lundgren ----`
7			`---- davidklun@gmail.com ----`
8			`---- ----`
9			`---------------------------------------------------------------------`
10			`---- ----`
11			`---- Copyright (C) 2009 David Lundgren ----`
12			`---- davidklun@gmail.com ----`
13			`---- ----`
14			`---- This source file may be used and distributed without ----`
15			`---- restriction provided that this copyright statement is not ----`
16			`---- removed from the file and that any derivative work contains ----`
17			`---- the original copyright notice and the associated disclaimer.----`
18			`---- ----`
19			---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
20			`---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----`
21			`---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----`
22			`---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----`
23			`---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----`
24			`---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----`
25			`---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----`
26			`---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----`
27			`---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----`
28			`---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----`
29			`---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----`
30			`---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----`
31			`---- POSSIBILITY OF SUCH DAMAGE. ----`
32			`---- ----`
33			`---------------------------------------------------------------------`
34
35			`LIBRARY ieee;`
36			`USE ieee.std_logic_1164.all;`
37			`USE ieee.std_logic_arith.all;`
38			`use ieee.std_logic_unsigned.all;`
39			`use ieee.std_logic_misc.all;`
40			`library work;`
41			`use work.fpupack.all;`
42
43			`ENTITY fpu_mul IS`
44
45			`PORT(`
46			`clk : IN std_logic;`
47			`rst : IN std_logic;`
48			`enable : IN std_logic;`
49			`opa : IN std_logic_vector (63 DOWNTO 0);`
50			`opb : IN std_logic_vector (63 DOWNTO 0);`
51			`sign : OUT std_logic;`
52			`product_7 : OUT std_logic_vector (55 DOWNTO 0);`
53			`exponent_5 : OUT std_logic_vector (11 DOWNTO 0)`
54			`);`
55
56			`END fpu_mul;`
57
58
59			`architecture rtl of fpu_mul is`
60
61			`signal product_shift : std_logic_vector(5 downto 0);`
62			`signal product_shift_2 : std_logic_vector(5 downto 0);`
63			`signal mantissa_a : std_logic_vector(51 downto 0);`
64			`signal mantissa_b : std_logic_vector(51 downto 0);`
65			`signal exponent_a : std_logic_vector(11 downto 0);`
66			`signal exponent_b : std_logic_vector(11 downto 0);`
67			`signal a_is_norm : std_logic;`
68			`signal b_is_norm : std_logic;`
69			`signal a_is_zero : std_logic;`
70			`signal b_is_zero : std_logic;`
71			`signal in_zero : std_logic;`
72			`signal exponent_terms : std_logic_vector(11 downto 0);`
73			`signal exponent_gt_expoffset : std_logic;`
74			`signal exponent_under : std_logic_vector(11 downto 0);`
75			`signal exponent_1 : std_logic_vector(11 downto 0);`
76			`signal exponent : std_logic_vector(11 downto 0);`
77			`signal exponent_2 : std_logic_vector(11 downto 0);`
78			`signal exponent_gt_prodshift : std_logic;`
79			`signal exponent_3 : std_logic_vector(11 downto 0);`
80			`signal exponent_4 : std_logic_vector(11 downto 0);`
81			`signal exponent_et_zero : std_logic;`
82			`signal mul_a : std_logic_vector(52 downto 0);`
83			`signal mul_b : std_logic_vector(52 downto 0);`
84			`signal product_a : std_logic_vector(40 downto 0);`
85			`signal product_b : std_logic_vector(40 downto 0);`
86			`signal product_c : std_logic_vector(40 downto 0);`
87			`signal product_d : std_logic_vector(25 downto 0);`
88			`signal product_e : std_logic_vector(33 downto 0);`
89			`signal product_f : std_logic_vector(33 downto 0);`
90			`signal product_g : std_logic_vector(35 downto 0);`
91			`signal product_h : std_logic_vector(28 downto 0);`
92			`signal product_i : std_logic_vector(28 downto 0);`
93			`signal product_j : std_logic_vector(30 downto 0);`
94			`signal sum_0 : std_logic_vector(41 downto 0);`
95			`signal sum_1 : std_logic_vector(35 downto 0);`
96			`signal sum_2 : std_logic_vector(41 downto 0);`
97			`signal sum_3 : std_logic_vector(35 downto 0);`
98			`signal sum_4 : std_logic_vector(36 downto 0);`
99			`signal sum_5 : std_logic_vector(27 downto 0);`
100			`signal sum_6 : std_logic_vector(29 downto 0);`
101			`signal sum_7 : std_logic_vector(36 downto 0);`
102			`signal sum_8 : std_logic_vector(30 downto 0);`
103			`signal product : std_logic_vector(105 downto 0);`
104			`signal product_1 : std_logic_vector(105 downto 0);`
105			`signal product_2 : std_logic_vector(105 downto 0);`
106			`signal product_3 : std_logic_vector(105 downto 0);`
107			`signal product_4 : std_logic_vector(105 downto 0);`
108			`signal product_5 : std_logic_vector(105 downto 0);`
109			`signal product_6 : std_logic_vector(105 downto 0);`
110			`signal product_lsb : std_logic;`
111
112			`begin`
113			`product_7 <= '0' & product_6(105 downto 52) & product_lsb;`
114			`exponent <= "000000000000";`
115			`process`
116			`begin`
117			`wait until clk'event and clk = '1';`
118			`if (rst = '1') then`
119			`sign <= '0';`
120			`mantissa_a <= (others =>'0');`
121			`mantissa_b <= (others =>'0');`
122			`exponent_a <= (others =>'0');`
123			`exponent_b <= (others =>'0');`
124			`a_is_norm <= '0';`
125			`b_is_norm <= '0';`
126			`a_is_zero <= '0';`
127			`b_is_zero <= '0';`
128			`in_zero <= '0';`
129			`exponent_terms <= (others =>'0');`
130			`exponent_gt_expoffset <= '0';`
131			`exponent_under <= (others =>'0');`
132			`exponent_1 <= (others =>'0');`
133			`exponent_2 <= (others =>'0');`
134			`exponent_gt_prodshift <= '0';`
135			`exponent_3 <= (others =>'0');`
136			`exponent_4 <= (others =>'0');`
137			`exponent_et_zero <= '0';`
138			`mul_a <= (others =>'0');`
139			`mul_b <= (others =>'0');`
140			`product_a <= (others =>'0');`
141			`product_b <= (others =>'0');`
142			`product_c <= (others =>'0');`
143			`product_d <= (others =>'0');`
144			`product_e <= (others =>'0');`
145			`product_f <= (others =>'0');`
146			`product_g <= (others =>'0');`
147			`product_h <= (others =>'0');`
148			`product_i <= (others =>'0');`
149			`product_j <= (others =>'0');`
150			`sum_0 <= (others =>'0');`
151			`sum_1 <= (others =>'0');`
152			`sum_2 <= (others =>'0');`
153			`sum_3 <= (others =>'0');`
154			`sum_4 <= (others =>'0');`
155			`sum_5 <= (others =>'0');`
156			`sum_6 <= (others =>'0');`
157			`sum_7 <= (others =>'0');`
158			`sum_8 <= (others =>'0');`
159			`product <= (others =>'0');`
160			`product_1 <= (others =>'0');`
161			`product_2 <= (others =>'0');`
162			`product_3 <= (others =>'0');`
163			`product_4 <= (others =>'0');`
164			`product_5 <= (others =>'0');`
165			`product_6 <= (others =>'0');`
166			`product_lsb <= '0';`
167			`exponent_5 <= (others =>'0');`
168			`product_shift <= (others =>'0');`
169			`product_shift_2 <= (others =>'0');`
170			`elsif (enable = '1') then`
171			`sign <= opa(63) xor opb(63);`
172			`exponent_a <= '0' & opa(62 downto 52);`
173			`exponent_b <= '0' & opb(62 downto 52);`
174			`mantissa_a <= opa(51 downto 0);`
175			`mantissa_b <= opb(51 downto 0);`
176			`a_is_norm <= or_reduce(exponent_a);`
177			`b_is_norm <= or_reduce(exponent_b);`
178			`a_is_zero <= not or_reduce(opa(62 downto 0));`
179			`b_is_zero <= not or_reduce(opb(62 downto 0));`
180			`in_zero <= a_is_zero or b_is_zero;`
181			`exponent_terms <= exponent_a + exponent_b + ( "0000000000" & not a_is_norm) +`
182			`("0000000000" & not b_is_norm);`
183			`if (exponent_terms > "001111111101") then`
184			`exponent_gt_expoffset <= '1';`
185			`else`
186			`exponent_gt_expoffset <= '0';`
187			`end if;`
188			`exponent_under <= "001111111110" - exponent_terms;`
189			`exponent_1 <= exponent_terms - "001111111110";`
190			`if (exponent_gt_expoffset = '1') then`
191			`exponent_2 <= exponent_1;`
192			`else`
193			`exponent_2 <= exponent;`
194			`end if;`
195			`if (exponent_2 > product_shift_2) then`
196			`exponent_gt_prodshift <= '1';`
197			`else`
198			`exponent_gt_prodshift <= '0';`
199			`end if;`
200			`exponent_3 <= exponent_2 - product_shift_2;`
201			`if (exponent_gt_prodshift = '1') then`
202			`exponent_4 <= exponent_3;`
203			`else`
204			`exponent_4 <= exponent;`
205			`end if;`
206			`if (exponent_4 = "000000000000") then`
207			`exponent_et_zero <= '1';`
208			`else`
209			`exponent_et_zero <= '0';`
210			`end if;`
211			`mul_a <= a_is_norm & mantissa_a;`
212			`mul_b <= b_is_norm & mantissa_b;`
213			`product_a <= mul_a(23 downto 0) * mul_b(16 downto 0);`
214			`product_b <= mul_a(23 downto 0) * mul_b(33 downto 17);`
215			`product_c <= mul_a(23 downto 0) * mul_b(50 downto 34);`
216			`product_d <= mul_a(23 downto 0) * mul_b(52 downto 51);`
217			`product_e <= mul_a(40 downto 24) * mul_b(16 downto 0);`
218			`product_f <= mul_a(40 downto 24) * mul_b(33 downto 17);`
219			`product_g <= mul_a(40 downto 24) * mul_b(52 downto 34);`
220			`product_h <= mul_a(52 downto 41) * mul_b(16 downto 0);`
221			`product_i <= mul_a(52 downto 41) * mul_b(33 downto 17);`
222			`product_j <= mul_a(52 downto 41) * mul_b(52 downto 34);`
223			`sum_0 <= product_a(40 downto 17) + ( '0' & product_b);`
224			`sum_1 <= ('0' & sum_0(41 downto 7)) + product_e;`
225			`sum_2 <= sum_1(35 downto 10) + ('0' & product_c);`
226			`sum_3 <= ( '0' & sum_2(41 downto 7)) + product_h;`
227			`sum_4 <= ( '0' & sum_3) + product_f;`
228			`sum_5 <= ('0' & sum_4(36 downto 10)) + product_d;`
229			`sum_6 <= sum_5(27 downto 7) + ('0' & product_i);`
230			`sum_7 <= sum_6 + ('0' & product_g);`
231			`sum_8 <= sum_7(36 downto 17) + product_j;`
232			`product <= sum_8 & sum_7(16 downto 0) & sum_5(6 downto 0) & sum_4(9 downto 0) & sum_2(6 downto 0) &`
233			`sum_1(9 downto 0) & sum_0(6 downto 0) & product_a(16 downto 0);`
234			`product_1 <= shr(product, exponent_under);`
235			`if (exponent_gt_prodshift = '1') then`
236			`product_5 <= product_3;`
237			`else`
238			`product_5 <= product_4;`
239			`end if;`
240			`if (exponent_gt_expoffset = '1') then`
241			`product_2 <= product;`
242			`else`
243			`product_2 <= product_1;`
244			`end if;`
245			`product_3 <= shl(product_2, product_shift_2);`
246			`product_4 <= shl(product_2, exponent_2);`
247			`if (exponent_gt_prodshift = '1') then`
248			`product_5 <= product_3;`
249			`else`
250			`product_5 <= product_4;`
251			`end if;`
252			`if (exponent_et_zero = '1') then`
253			`product_6 <= shr(product_5, conv_std_logic_vector('1', 106));`
254			`else`
255			`product_6 <= product_5;`
256			`end if;`
257			`product_lsb <= or_reduce(product_6(51 downto 0));`
258			`if (in_zero = '1') then`
259			`exponent_5 <= "000000000000";`
260			`else`
261			`exponent_5 <= exponent_4;`
262			`end if;`
263			`product_shift <= count_zeros_mul(product(105 downto 0));`
264			`product_shift_2 <= product_shift;`
265			`end if;`
266			`end process;`
267			`end rtl;`