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[/] [fpu_double/] [trunk/] [comppack.vhd] - Blame information for rev 5

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Line No. Rev Author Line
1 2 davidklun
---------------------------------------------------------------------
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----                                                             ----
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----  FPU                                                        ----
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----  Floating Point Unit (Double precision)                     ----
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----                                                             ----
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----  Author: David Lundgren                                     ----
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----          davidklun@gmail.com                                ----
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----                                                             ----
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---------------------------------------------------------------------
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----                                                             ----
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---- Copyright (C) 2009 David Lundgren                           ----
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----                  davidklun@gmail.com                        ----
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----                                                             ----
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---- This source file may be used and distributed without        ----
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---- restriction provided that this copyright statement is not   ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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----                                                             ----
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----     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ----
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---- LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ----
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---- POSSIBILITY OF SUCH DAMAGE.                                 ----
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----                                                             ----
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---------------------------------------------------------------------
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library  ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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library work;
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use work.fpupack.all;
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package comppack is
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--- Component Declarations ---  
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        component fpu_add is
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         PORT(
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      clk : IN     std_logic;
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      rst : IN     std_logic;
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      enable  : IN     std_logic;
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      opa : IN     std_logic_vector (63 DOWNTO 0);
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      opb : IN     std_logic_vector (63 DOWNTO 0);
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      sign : OUT    std_logic;
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      sum_3 : OUT    std_logic_vector (55 DOWNTO 0);
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      exponent_2 : OUT    std_logic_vector (10 DOWNTO 0)
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   );
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        end component;
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        component fpu_sub is
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                 PORT(
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          clk : IN     std_logic;
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      rst : IN     std_logic;
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      enable  : IN     std_logic;
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      opa : IN     std_logic_vector (63 DOWNTO 0);
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      opb : IN     std_logic_vector (63 DOWNTO 0);
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      fpu_op : IN     std_logic_vector (2 DOWNTO 0);
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      sign : OUT    std_logic;
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      diff_2 : OUT    std_logic_vector (55 DOWNTO 0);
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      exponent_2 : OUT    std_logic_vector (10 DOWNTO 0)
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   );
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        end component;
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        component fpu_mul is
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        port(
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                    clk : IN     std_logic;
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                rst : IN     std_logic;
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                enable  : IN     std_logic;
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                opa : IN     std_logic_vector (63 DOWNTO 0);
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                opb : IN     std_logic_vector (63 DOWNTO 0);
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                sign : OUT    std_logic;
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                product_7 : OUT    std_logic_vector (55 DOWNTO 0);
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                exponent_5 : OUT    std_logic_vector (11 DOWNTO 0)
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                );
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        end component;
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        component fpu_div is
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        port(
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                        clk, rst, enable : IN     std_logic;
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                opa, opb : IN     std_logic_vector (63 DOWNTO 0);
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                sign : OUT    std_logic;
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                mantissa_7 : OUT    std_logic_vector (55 DOWNTO 0);
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                exponent_out : OUT    std_logic_vector (11 DOWNTO 0)
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                         );
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        end component;
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        component fpu_round is
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        port(
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                                clk, rst, enable : IN     std_logic;
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                        round_mode : IN     std_logic_vector (1 DOWNTO 0);
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                        sign_term : IN    std_logic;
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                        mantissa_term : IN     std_logic_vector (55 DOWNTO 0);
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                        exponent_term : IN     std_logic_vector (11 DOWNTO 0);
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                        round_out : OUT    std_logic_vector (63 DOWNTO 0);
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                        exponent_final : OUT    std_logic_vector (11 DOWNTO 0)
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                         );
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        end component;
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        component fpu_exceptions is
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        port(
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                          clk, rst, enable : IN     std_logic;
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                          rmode : IN     std_logic_vector (1 DOWNTO 0);
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                          opa, opb, in_except : IN     std_logic_vector (63 DOWNTO 0);
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                          exponent_in : IN     std_logic_vector (11 DOWNTO 0);
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                          mantissa_in : IN     std_logic_vector (1 DOWNTO 0);
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                          fpu_op : IN     std_logic_vector (2 DOWNTO 0);
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                          out_fp : OUT    std_logic_vector (63 DOWNTO 0);
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                          ex_enable, underflow, overflow, inexact : OUT    std_logic;
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                          exception, invalid : OUT    std_logic
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                );
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        end component;
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end comppack;

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