| 1 |
2 |
davidklun |
---------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- FPU ----
|
| 4 |
|
|
---- Floating Point Unit (Double precision) ----
|
| 5 |
|
|
---- ----
|
| 6 |
|
|
---- Author: David Lundgren ----
|
| 7 |
|
|
---- davidklun@gmail.com ----
|
| 8 |
|
|
---- ----
|
| 9 |
|
|
---------------------------------------------------------------------
|
| 10 |
|
|
---- ----
|
| 11 |
|
|
---- Copyright (C) 2009 David Lundgren ----
|
| 12 |
|
|
---- davidklun@gmail.com ----
|
| 13 |
|
|
---- ----
|
| 14 |
|
|
---- This source file may be used and distributed without ----
|
| 15 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 16 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 17 |
|
|
---- the original copyright notice and the associated disclaimer.----
|
| 18 |
|
|
---- ----
|
| 19 |
|
|
---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
|
| 20 |
|
|
---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
|
| 21 |
|
|
---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
|
| 22 |
|
|
---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
|
| 23 |
|
|
---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
|
| 24 |
|
|
---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
|
| 25 |
|
|
---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
|
| 26 |
|
|
---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
|
| 27 |
|
|
---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
|
| 28 |
|
|
---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
|
| 29 |
|
|
---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
|
| 30 |
|
|
---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
|
| 31 |
|
|
---- POSSIBILITY OF SUCH DAMAGE. ----
|
| 32 |
|
|
---- ----
|
| 33 |
|
|
---------------------------------------------------------------------
|
| 34 |
|
|
|
| 35 |
|
|
LIBRARY ieee;
|
| 36 |
|
|
USE ieee.std_logic_1164.all;
|
| 37 |
|
|
USE ieee.std_logic_arith.all;
|
| 38 |
|
|
use ieee.std_logic_unsigned.all;
|
| 39 |
|
|
use ieee.std_logic_misc.all;
|
| 40 |
|
|
library work;
|
| 41 |
|
|
use work.fpupack.all;
|
| 42 |
|
|
|
| 43 |
|
|
ENTITY fpu_sub IS
|
| 44 |
|
|
|
| 45 |
|
|
PORT(
|
| 46 |
|
|
clk : IN std_logic;
|
| 47 |
|
|
rst : IN std_logic;
|
| 48 |
|
|
enable : IN std_logic;
|
| 49 |
|
|
opa : IN std_logic_vector (63 DOWNTO 0);
|
| 50 |
|
|
opb : IN std_logic_vector (63 DOWNTO 0);
|
| 51 |
|
|
fpu_op : IN std_logic_vector (2 DOWNTO 0);
|
| 52 |
|
|
sign : OUT std_logic;
|
| 53 |
|
|
diff_2 : OUT std_logic_vector (55 DOWNTO 0);
|
| 54 |
|
|
exponent_2 : OUT std_logic_vector (10 DOWNTO 0)
|
| 55 |
|
|
);
|
| 56 |
|
|
|
| 57 |
|
|
-- Declarations
|
| 58 |
|
|
|
| 59 |
|
|
END fpu_sub;
|
| 60 |
|
|
|
| 61 |
|
|
|
| 62 |
|
|
architecture rtl of fpu_sub is
|
| 63 |
|
|
|
| 64 |
|
|
signal fpu_op_add : std_logic;
|
| 65 |
|
|
signal diff_shift : std_logic_vector(5 downto 0);
|
| 66 |
|
|
signal diff_shift_2 : std_logic_vector(5 downto 0);
|
| 67 |
|
|
signal exponent_a : std_logic_vector(10 downto 0);
|
| 68 |
|
|
signal exponent_b : std_logic_vector(10 downto 0);
|
| 69 |
|
|
signal mantissa_a : std_logic_vector(51 downto 0);
|
| 70 |
|
|
signal mantissa_b : std_logic_vector(51 downto 0);
|
| 71 |
|
|
signal expa_gt_expb : std_logic;
|
| 72 |
|
|
signal expa_et_expb : std_logic;
|
| 73 |
|
|
signal mana_gtet_manb : std_logic;
|
| 74 |
|
|
signal a_gtet_b : std_logic;
|
| 75 |
|
|
signal exponent_small : std_logic_vector(10 downto 0);
|
| 76 |
|
|
signal exponent_large : std_logic_vector(10 downto 0);
|
| 77 |
|
|
signal mantissa_small : std_logic_vector(51 downto 0);
|
| 78 |
|
|
signal mantissa_large : std_logic_vector(51 downto 0);
|
| 79 |
|
|
signal small_is_denorm : std_logic;
|
| 80 |
|
|
signal large_is_denorm : std_logic;
|
| 81 |
|
|
signal large_norm_small_denorm : std_logic;
|
| 82 |
|
|
signal small_is_nonzero : std_logic;
|
| 83 |
|
|
signal exponent_diff : std_logic_vector(10 downto 0);
|
| 84 |
|
|
signal minuend : std_logic_vector(54 downto 0);
|
| 85 |
|
|
signal subtrahend : std_logic_vector(54 downto 0);
|
| 86 |
|
|
signal subtra_shift : std_logic_vector(54 downto 0);
|
| 87 |
|
|
signal subtra_shift_nonzero : std_logic;
|
| 88 |
|
|
signal subtra_fraction_enable : std_logic;
|
| 89 |
|
|
signal subtra_shift_2 : std_logic_vector(54 downto 0);
|
| 90 |
|
|
signal subtra_shift_3 : std_logic_vector(54 downto 0);
|
| 91 |
|
|
signal diff : std_logic_vector(54 downto 0);
|
| 92 |
|
|
signal diffshift_gt_exponent : std_logic;
|
| 93 |
|
|
signal diffshift_et_55 : std_logic; -- when the difference = 0
|
| 94 |
|
|
signal diff_1 : std_logic_vector(54 downto 0);
|
| 95 |
|
|
signal exponent : std_logic_vector(10 downto 0);
|
| 96 |
|
|
signal in_norm_out_denorm : std_logic;
|
| 97 |
|
|
|
| 98 |
|
|
begin
|
| 99 |
|
|
|
| 100 |
|
|
subtra_shift_nonzero <= or_reduce(subtra_shift);
|
| 101 |
|
|
subtra_fraction_enable <= small_is_nonzero and not subtra_shift_nonzero;
|
| 102 |
|
|
subtra_shift_2 <= "0000000000000000000000000000000000000000000000000000001";
|
| 103 |
|
|
in_norm_out_denorm <= or_reduce(exponent_large) and not or_reduce(exponent);
|
| 104 |
|
|
fpu_op_add <= '1' when fpu_op = "000" else '0';
|
| 105 |
|
|
|
| 106 |
|
|
process
|
| 107 |
|
|
begin
|
| 108 |
|
|
wait until clk'event and clk = '1';
|
| 109 |
|
|
if (rst = '1') then
|
| 110 |
|
|
exponent_a <= (others =>'0');
|
| 111 |
|
|
exponent_b <= (others =>'0');
|
| 112 |
|
|
mantissa_a <= (others =>'0');
|
| 113 |
|
|
mantissa_b <= (others =>'0');
|
| 114 |
|
|
expa_gt_expb <= '0';
|
| 115 |
|
|
expa_et_expb <= '0';
|
| 116 |
|
|
mana_gtet_manb <= '0';
|
| 117 |
|
|
a_gtet_b <= '0';
|
| 118 |
|
|
exponent_small <= (others =>'0');
|
| 119 |
|
|
exponent_large <= (others =>'0');
|
| 120 |
|
|
mantissa_small <= (others =>'0');
|
| 121 |
|
|
mantissa_large <= (others =>'0');
|
| 122 |
|
|
sign <= '0';
|
| 123 |
|
|
small_is_denorm <= '0';
|
| 124 |
|
|
large_is_denorm <= '0';
|
| 125 |
|
|
large_norm_small_denorm <= '0';
|
| 126 |
|
|
small_is_nonzero <= '0';
|
| 127 |
|
|
exponent_diff <= (others =>'0');
|
| 128 |
|
|
minuend <= (others =>'0');
|
| 129 |
|
|
subtrahend <= (others =>'0');
|
| 130 |
|
|
subtra_shift <= (others =>'0');
|
| 131 |
|
|
subtra_shift_3 <= (others =>'0');
|
| 132 |
8 |
davidklun |
diff_shift <= (others =>'0');
|
| 133 |
2 |
davidklun |
diff_shift_2 <= (others =>'0');
|
| 134 |
|
|
diff <= (others =>'0');
|
| 135 |
|
|
diffshift_gt_exponent <= '0';
|
| 136 |
|
|
diffshift_et_55 <= '0';
|
| 137 |
|
|
diff_1 <= (others =>'0');
|
| 138 |
|
|
exponent <= (others =>'0');
|
| 139 |
|
|
exponent_2 <= (others =>'0');
|
| 140 |
|
|
diff_2 <= (others =>'0');
|
| 141 |
|
|
elsif (enable = '1') then
|
| 142 |
|
|
exponent_a <= opa(62 downto 52);
|
| 143 |
|
|
exponent_b <= opb(62 downto 52);
|
| 144 |
|
|
mantissa_a <= opa(51 downto 0);
|
| 145 |
|
|
mantissa_b <= opb(51 downto 0);
|
| 146 |
|
|
if (exponent_a > exponent_b) then
|
| 147 |
|
|
expa_gt_expb <= '1';
|
| 148 |
|
|
else
|
| 149 |
|
|
expa_gt_expb <= '0';
|
| 150 |
|
|
end if;
|
| 151 |
|
|
if (exponent_a = exponent_b) then
|
| 152 |
|
|
expa_et_expb <= '1';
|
| 153 |
|
|
else
|
| 154 |
|
|
expa_et_expb <= '0';
|
| 155 |
|
|
end if;
|
| 156 |
|
|
if (mantissa_a >= mantissa_b) then
|
| 157 |
|
|
mana_gtet_manb <= '1';
|
| 158 |
|
|
else
|
| 159 |
|
|
mana_gtet_manb <= '0';
|
| 160 |
|
|
end if;
|
| 161 |
|
|
a_gtet_b <= expa_gt_expb or (expa_et_expb and mana_gtet_manb);
|
| 162 |
|
|
if (a_gtet_b = '1') then
|
| 163 |
|
|
exponent_small <= exponent_b;
|
| 164 |
|
|
exponent_large <= exponent_a;
|
| 165 |
|
|
mantissa_small <= mantissa_b;
|
| 166 |
|
|
mantissa_large <= mantissa_a;
|
| 167 |
|
|
sign <= opa(63);
|
| 168 |
|
|
else
|
| 169 |
|
|
exponent_small <= exponent_a;
|
| 170 |
|
|
exponent_large <= exponent_b;
|
| 171 |
|
|
mantissa_small <= mantissa_a;
|
| 172 |
|
|
mantissa_large <= mantissa_b;
|
| 173 |
|
|
sign <= (not opb(63)) xor fpu_op_add;
|
| 174 |
|
|
end if;
|
| 175 |
|
|
if (exponent_small > 0) then
|
| 176 |
|
|
small_is_denorm <= '0';
|
| 177 |
|
|
else
|
| 178 |
|
|
small_is_denorm <= '1';
|
| 179 |
|
|
end if;
|
| 180 |
|
|
if (exponent_large > 0) then
|
| 181 |
|
|
large_is_denorm <= '0';
|
| 182 |
|
|
else
|
| 183 |
|
|
large_is_denorm <= '1';
|
| 184 |
|
|
end if;
|
| 185 |
|
|
if (small_is_denorm = '1' and large_is_denorm = '0') then
|
| 186 |
|
|
large_norm_small_denorm <= '1';
|
| 187 |
|
|
else
|
| 188 |
|
|
large_norm_small_denorm <= '0';
|
| 189 |
|
|
end if;
|
| 190 |
|
|
small_is_nonzero <= (not small_is_denorm) or or_reduce(mantissa_small);
|
| 191 |
|
|
exponent_diff <= exponent_large - exponent_small - large_norm_small_denorm;
|
| 192 |
|
|
minuend <= not large_is_denorm & mantissa_large & "00";
|
| 193 |
|
|
subtrahend <= not small_is_denorm & mantissa_small & "00";
|
| 194 |
|
|
subtra_shift <= shr(subtrahend, exponent_diff);
|
| 195 |
|
|
if (subtra_fraction_enable = '1') then
|
| 196 |
|
|
subtra_shift_3 <= subtra_shift_2;
|
| 197 |
|
|
else
|
| 198 |
|
|
subtra_shift_3 <= subtra_shift;
|
| 199 |
|
|
end if;
|
| 200 |
|
|
diff <= minuend - subtra_shift_3;
|
| 201 |
|
|
diff_shift <= count_l_zeros(diff(54 downto 0));
|
| 202 |
|
|
diff_shift_2 <= diff_shift;
|
| 203 |
|
|
if (diff_shift_2 > exponent_large) then
|
| 204 |
|
|
diffshift_gt_exponent <= '1';
|
| 205 |
|
|
else
|
| 206 |
|
|
diffshift_gt_exponent <= '0';
|
| 207 |
|
|
end if;
|
| 208 |
|
|
if (diff_shift_2 = "0110111") then -- 55
|
| 209 |
|
|
diffshift_et_55 <= '1';
|
| 210 |
|
|
else
|
| 211 |
|
|
diffshift_et_55 <= '0';
|
| 212 |
|
|
end if;
|
| 213 |
|
|
if (diffshift_gt_exponent = '1') then
|
| 214 |
|
|
diff_1 <= shl(diff, exponent_large);
|
| 215 |
|
|
exponent <= "00000000000";
|
| 216 |
|
|
else
|
| 217 |
|
|
diff_1 <= shl(diff, diff_shift_2);
|
| 218 |
|
|
exponent <= exponent_large - diff_shift_2;
|
| 219 |
|
|
end if;
|
| 220 |
|
|
if (diffshift_et_55 = '1') then
|
| 221 |
|
|
exponent_2 <= "00000000000";
|
| 222 |
|
|
else
|
| 223 |
|
|
exponent_2 <= exponent;
|
| 224 |
|
|
end if;
|
| 225 |
|
|
if (in_norm_out_denorm = '1') then
|
| 226 |
|
|
diff_2 <= '0' & shr(diff_1,conv_std_logic_vector('1', 55));
|
| 227 |
|
|
else
|
| 228 |
|
|
diff_2 <= '0' & diff_1;
|
| 229 |
|
|
end if;
|
| 230 |
|
|
end if;
|
| 231 |
|
|
end process;
|
| 232 |
|
|
|
| 233 |
|
|
end rtl;
|
| 234 |
|
|
|
| 235 |
|
|
|
