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[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [adder/] [fpadd_pipeline.vhd] - Blame information for rev 5

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-- VHDL Entity work.FPadd.symbol
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- 2003-2004. V1.0
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY FPadd IS
   PORT(
      ADD_SUB : IN     std_logic;
      FP_A    : IN     std_logic_vector (31 DOWNTO 0);
      FP_B    : IN     std_logic_vector (31 DOWNTO 0);
      clk     : IN     std_logic;
      FP_Z    : OUT    std_logic_vector (31 DOWNTO 0)
   );
 
-- Declarations
 
END FPadd ;
 
--
-- VHDL Architecture work.FPadd.pipeline
--
-- Created by
-- Guillermo Marcus, gmarcus@ieee.org
-- using Mentor Graphics FPGA Advantage tools.
--
-- Visit "http://fpga.mty.itesm.mx" for more info.
--
-- Copyright 2003-2004. V1.0
--
 
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ARCHITECTURE pipeline OF FPadd IS
 
   -- Architecture declarations
 
   -- Internal signal declarations
   SIGNAL ADD_SUB_out      : std_logic;
   SIGNAL A_EXP            : std_logic_vector(7 DOWNTO 0);
   SIGNAL A_SIGN           : std_logic;
   SIGNAL A_SIGN_stage2    : std_logic;
   SIGNAL A_SIGN_stage3    : std_logic;
   SIGNAL A_align          : std_logic_vector(28 DOWNTO 0);
   SIGNAL A_in             : std_logic_vector(28 DOWNTO 0);
   SIGNAL A_isINF          : std_logic;
   SIGNAL A_isNaN          : std_logic;
   SIGNAL A_isZ            : std_logic;
   SIGNAL B_EXP            : std_logic_vector(7 DOWNTO 0);
   SIGNAL B_XSIGN          : std_logic;
   SIGNAL B_XSIGN_stage2   : std_logic;
   SIGNAL B_XSIGN_stage3   : std_logic;
   SIGNAL B_align          : std_logic_vector(28 DOWNTO 0);
   SIGNAL B_in             : std_logic_vector(28 DOWNTO 0);
   SIGNAL B_isINF          : std_logic;
   SIGNAL B_isNaN          : std_logic;
   SIGNAL B_isZ            : std_logic;
   SIGNAL EXP_base         : std_logic_vector(7 DOWNTO 0);
   SIGNAL EXP_base_stage2  : std_logic_vector(7 DOWNTO 0);
   SIGNAL EXP_diff         : std_logic_vector(8 DOWNTO 0);
   SIGNAL EXP_norm         : std_logic_vector(7 DOWNTO 0);
   SIGNAL OV               : std_logic;
   SIGNAL OV_stage4        : std_logic;
   SIGNAL SIG_norm         : std_logic_vector(27 DOWNTO 0);
   SIGNAL SIG_norm2        : std_logic_vector(27 DOWNTO 0);
   SIGNAL Z_EXP            : std_logic_vector(7 DOWNTO 0);
   SIGNAL Z_SIGN           : std_logic;
   SIGNAL Z_SIGN_stage4    : std_logic;
   SIGNAL add_out          : std_logic_vector(28 DOWNTO 0);
   SIGNAL cin              : std_logic;
   SIGNAL cin_sub          : std_logic;
   SIGNAL invert_A         : std_logic;
   SIGNAL invert_B         : std_logic;
   SIGNAL isINF_tab        : std_logic;
   SIGNAL isINF_tab_stage2 : std_logic;
   SIGNAL isINF_tab_stage3 : std_logic;
   SIGNAL isINF_tab_stage4 : std_logic;
   SIGNAL isNaN            : std_logic;
   SIGNAL isNaN_stage2     : std_logic;
   SIGNAL isNaN_stage3     : std_logic;
   SIGNAL isNaN_stage4     : std_logic;
   SIGNAL isZ_tab          : std_logic;
   SIGNAL isZ_tab_stage2   : std_logic;
   SIGNAL isZ_tab_stage3   : std_logic;
   SIGNAL isZ_tab_stage4   : std_logic;
   SIGNAL zero             : std_logic;
   SIGNAL zero_stage4      : std_logic;
 
 
   -- Component Declarations
   COMPONENT FPadd_stage1
   PORT (
      ADD_SUB     : IN     std_logic ;
      FP_A        : IN     std_logic_vector (31 DOWNTO 0);
      FP_B        : IN     std_logic_vector (31 DOWNTO 0);
      clk         : IN     std_logic ;
      ADD_SUB_out : OUT    std_logic ;
      A_EXP       : OUT    std_logic_vector (7 DOWNTO 0);
      A_SIGN      : OUT    std_logic ;
      A_in        : OUT    std_logic_vector (28 DOWNTO 0);
      A_isINF     : OUT    std_logic ;
      A_isNaN     : OUT    std_logic ;
      A_isZ       : OUT    std_logic ;
      B_EXP       : OUT    std_logic_vector (7 DOWNTO 0);
      B_XSIGN     : OUT    std_logic ;
      B_in        : OUT    std_logic_vector (28 DOWNTO 0);
      B_isINF     : OUT    std_logic ;
      B_isNaN     : OUT    std_logic ;
      B_isZ       : OUT    std_logic ;
      EXP_diff    : OUT    std_logic_vector (8 DOWNTO 0);
      cin_sub     : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT FPadd_stage2
   PORT (
      ADD_SUB_out      : IN     std_logic ;
      A_EXP            : IN     std_logic_vector (7 DOWNTO 0);
      A_SIGN           : IN     std_logic ;
      A_in             : IN     std_logic_vector (28 DOWNTO 0);
      A_isINF          : IN     std_logic ;
      A_isNaN          : IN     std_logic ;
      A_isZ            : IN     std_logic ;
      B_EXP            : IN     std_logic_vector (7 DOWNTO 0);
      B_XSIGN          : IN     std_logic ;
      B_in             : IN     std_logic_vector (28 DOWNTO 0);
      B_isINF          : IN     std_logic ;
      B_isNaN          : IN     std_logic ;
      B_isZ            : IN     std_logic ;
      EXP_diff         : IN     std_logic_vector (8 DOWNTO 0);
      cin_sub          : IN     std_logic ;
      clk              : IN     std_logic ;
      A_SIGN_stage2    : OUT    std_logic ;
      A_align          : OUT    std_logic_vector (28 DOWNTO 0);
      B_XSIGN_stage2   : OUT    std_logic ;
      B_align          : OUT    std_logic_vector (28 DOWNTO 0);
      EXP_base_stage2  : OUT    std_logic_vector (7 DOWNTO 0);
      cin              : OUT    std_logic ;
      invert_A         : OUT    std_logic ;
      invert_B         : OUT    std_logic ;
      isINF_tab_stage2 : OUT    std_logic ;
      isNaN_stage2     : OUT    std_logic ;
      isZ_tab_stage2   : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT FPadd_stage3
   PORT (
      A_SIGN_stage2    : IN     std_logic ;
      A_align          : IN     std_logic_vector (28 DOWNTO 0);
      B_XSIGN_stage2   : IN     std_logic ;
      B_align          : IN     std_logic_vector (28 DOWNTO 0);
      EXP_base_stage2  : IN     std_logic_vector (7 DOWNTO 0);
      cin              : IN     std_logic ;
      clk              : IN     std_logic ;
      invert_A         : IN     std_logic ;
      invert_B         : IN     std_logic ;
      isINF_tab_stage2 : IN     std_logic ;
      isNaN_stage2     : IN     std_logic ;
      isZ_tab_stage2   : IN     std_logic ;
      A_SIGN_stage3    : OUT    std_logic ;
      B_XSIGN_stage3   : OUT    std_logic ;
      EXP_base         : OUT    std_logic_vector (7 DOWNTO 0);
      add_out          : OUT    std_logic_vector (28 DOWNTO 0);
      isINF_tab_stage3 : OUT    std_logic ;
      isNaN_stage3     : OUT    std_logic ;
      isZ_tab_stage3   : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT FPadd_stage4
   PORT (
      A_SIGN_stage3    : IN     std_logic ;
      B_XSIGN_stage3   : IN     std_logic ;
      EXP_base         : IN     std_logic_vector (7 DOWNTO 0);
      add_out          : IN     std_logic_vector (28 DOWNTO 0);
      clk              : IN     std_logic ;
      isINF_tab_stage3 : IN     std_logic ;
      isNaN_stage3     : IN     std_logic ;
      isZ_tab_stage3   : IN     std_logic ;
      EXP_norm         : OUT    std_logic_vector (7 DOWNTO 0);
      OV_stage4        : OUT    std_logic ;
      SIG_norm         : OUT    std_logic_vector (27 DOWNTO 0);
      Z_SIGN_stage4    : OUT    std_logic ;
      isINF_tab_stage4 : OUT    std_logic ;
      isNaN_stage4     : OUT    std_logic ;
      isZ_tab_stage4   : OUT    std_logic ;
      zero_stage4      : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT FPadd_stage5
   PORT (
      EXP_norm         : IN     std_logic_vector (7 DOWNTO 0);
      OV_stage4        : IN     std_logic ;
      SIG_norm         : IN     std_logic_vector (27 DOWNTO 0);
      Z_SIGN_stage4    : IN     std_logic ;
      clk              : IN     std_logic ;
      isINF_tab_stage4 : IN     std_logic ;
      isNaN_stage4     : IN     std_logic ;
      isZ_tab_stage4   : IN     std_logic ;
      zero_stage4      : IN     std_logic ;
      OV               : OUT    std_logic ;
      SIG_norm2        : OUT    std_logic_vector (27 DOWNTO 0);
      Z_EXP            : OUT    std_logic_vector (7 DOWNTO 0);
      Z_SIGN           : OUT    std_logic ;
      isINF_tab        : OUT    std_logic ;
      isNaN            : OUT    std_logic ;
      isZ_tab          : OUT    std_logic ;
      zero             : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT FPadd_stage6
   PORT (
      OV        : IN     std_logic ;
      SIG_norm2 : IN     std_logic_vector (27 DOWNTO 0);
      Z_EXP     : IN     std_logic_vector (7 DOWNTO 0);
      Z_SIGN    : IN     std_logic ;
      clk       : IN     std_logic ;
      isINF_tab : IN     std_logic ;
      isNaN     : IN     std_logic ;
      isZ_tab   : IN     std_logic ;
      zero      : IN     std_logic ;
      FP_Z      : OUT    std_logic_vector (31 DOWNTO 0)
   );
   END COMPONENT;
 
   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : FPadd_stage1 USE ENTITY work.FPadd_stage1;
   FOR ALL : FPadd_stage2 USE ENTITY work.FPadd_stage2;
   FOR ALL : FPadd_stage3 USE ENTITY work.FPadd_stage3;
   FOR ALL : FPadd_stage4 USE ENTITY work.FPadd_stage4;
   FOR ALL : FPadd_stage5 USE ENTITY work.FPadd_stage5;
   FOR ALL : FPadd_stage6 USE ENTITY work.FPadd_stage6;
   -- pragma synthesis_on
 
 
BEGIN
 
   -- Instance port mappings.
   I1 : FPadd_stage1
      PORT MAP (
         ADD_SUB     => ADD_SUB,
         FP_A        => FP_A,
         FP_B        => FP_B,
         clk         => clk,
         ADD_SUB_out => ADD_SUB_out,
         A_EXP       => A_EXP,
         A_SIGN      => A_SIGN,
         A_in        => A_in,
         A_isINF     => A_isINF,
         A_isNaN     => A_isNaN,
         A_isZ       => A_isZ,
         B_EXP       => B_EXP,
         B_XSIGN     => B_XSIGN,
         B_in        => B_in,
         B_isINF     => B_isINF,
         B_isNaN     => B_isNaN,
         B_isZ       => B_isZ,
         EXP_diff    => EXP_diff,
         cin_sub     => cin_sub
      );
   I2 : FPadd_stage2
      PORT MAP (
         ADD_SUB_out      => ADD_SUB_out,
         A_EXP            => A_EXP,
         A_SIGN           => A_SIGN,
         A_in             => A_in,
         A_isINF          => A_isINF,
         A_isNaN          => A_isNaN,
         A_isZ            => A_isZ,
         B_EXP            => B_EXP,
         B_XSIGN          => B_XSIGN,
         B_in             => B_in,
         B_isINF          => B_isINF,
         B_isNaN          => B_isNaN,
         B_isZ            => B_isZ,
         EXP_diff         => EXP_diff,
         cin_sub          => cin_sub,
         clk              => clk,
         A_SIGN_stage2    => A_SIGN_stage2,
         A_align          => A_align,
         B_XSIGN_stage2   => B_XSIGN_stage2,
         B_align          => B_align,
         EXP_base_stage2  => EXP_base_stage2,
         cin              => cin,
         invert_A         => invert_A,
         invert_B         => invert_B,
         isINF_tab_stage2 => isINF_tab_stage2,
         isNaN_stage2     => isNaN_stage2,
         isZ_tab_stage2   => isZ_tab_stage2
      );
   I3 : FPadd_stage3
      PORT MAP (
         A_SIGN_stage2    => A_SIGN_stage2,
         A_align          => A_align,
         B_XSIGN_stage2   => B_XSIGN_stage2,
         B_align          => B_align,
         EXP_base_stage2  => EXP_base_stage2,
         cin              => cin,
         clk              => clk,
         invert_A         => invert_A,
         invert_B         => invert_B,
         isINF_tab_stage2 => isINF_tab_stage2,
         isNaN_stage2     => isNaN_stage2,
         isZ_tab_stage2   => isZ_tab_stage2,
         A_SIGN_stage3    => A_SIGN_stage3,
         B_XSIGN_stage3   => B_XSIGN_stage3,
         EXP_base         => EXP_base,
         add_out          => add_out,
         isINF_tab_stage3 => isINF_tab_stage3,
         isNaN_stage3     => isNaN_stage3,
         isZ_tab_stage3   => isZ_tab_stage3
      );
   I4 : FPadd_stage4
      PORT MAP (
         A_SIGN_stage3    => A_SIGN_stage3,
         B_XSIGN_stage3   => B_XSIGN_stage3,
         EXP_base         => EXP_base,
         add_out          => add_out,
         clk              => clk,
         isINF_tab_stage3 => isINF_tab_stage3,
         isNaN_stage3     => isNaN_stage3,
         isZ_tab_stage3   => isZ_tab_stage3,
         EXP_norm         => EXP_norm,
         OV_stage4        => OV_stage4,
         SIG_norm         => SIG_norm,
         Z_SIGN_stage4    => Z_SIGN_stage4,
         isINF_tab_stage4 => isINF_tab_stage4,
         isNaN_stage4     => isNaN_stage4,
         isZ_tab_stage4   => isZ_tab_stage4,
         zero_stage4      => zero_stage4
      );
   I5 : FPadd_stage5
      PORT MAP (
         EXP_norm         => EXP_norm,
         OV_stage4        => OV_stage4,
         SIG_norm         => SIG_norm,
         Z_SIGN_stage4    => Z_SIGN_stage4,
         clk              => clk,
         isINF_tab_stage4 => isINF_tab_stage4,
         isNaN_stage4     => isNaN_stage4,
         isZ_tab_stage4   => isZ_tab_stage4,
         zero_stage4      => zero_stage4,
         OV               => OV,
         SIG_norm2        => SIG_norm2,
         Z_EXP            => Z_EXP,
         Z_SIGN           => Z_SIGN,
         isINF_tab        => isINF_tab,
         isNaN            => isNaN,
         isZ_tab          => isZ_tab,
         zero             => zero
      );
   I6 : FPadd_stage6
      PORT MAP (
         OV        => OV,
         SIG_norm2 => SIG_norm2,
         Z_EXP     => Z_EXP,
         Z_SIGN    => Z_SIGN,
         clk       => clk,
         isINF_tab => isINF_tab,
         isNaN     => isNaN,
         isZ_tab   => isZ_tab,
         zero      => zero,
         FP_Z      => FP_Z
      );
 
END pipeline;

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[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [adder/] [fpadd_pipeline.vhd] - Blame information for rev 5

Line No.	Rev	Author	Line
1	4	gmarcus	`-- VHDL Entity work.FPadd.symbol`
2	3	gmarcus	`--`
3			`-- Created by`
4			`-- Guillermo Marcus, gmarcus@ieee.org`
5			`-- using Mentor Graphics FPGA Advantage tools.`
6			`--`
7			`-- Visit "http://fpga.mty.itesm.mx" for more info.`
8			`--`
9			`-- 2003-2004. V1.0`
10			`--`
11
12			`LIBRARY ieee;`
13			`USE ieee.std_logic_1164.all;`
14			`USE ieee.std_logic_arith.all;`
15
16			`ENTITY FPadd IS`
17			`PORT(`
18			`ADD_SUB : IN std_logic;`
19			`FP_A : IN std_logic_vector (31 DOWNTO 0);`
20			`FP_B : IN std_logic_vector (31 DOWNTO 0);`
21			`clk : IN std_logic;`
22			`FP_Z : OUT std_logic_vector (31 DOWNTO 0)`
23			`);`
24
25			`-- Declarations`
26
27			`END FPadd ;`
28
29			`--`
30	4	gmarcus	`-- VHDL Architecture work.FPadd.pipeline`
31	3	gmarcus	`--`
32			`-- Created by`
33			`-- Guillermo Marcus, gmarcus@ieee.org`
34			`-- using Mentor Graphics FPGA Advantage tools.`
35			`--`
36			`-- Visit "http://fpga.mty.itesm.mx" for more info.`
37			`--`
38			`-- Copyright 2003-2004. V1.0`
39			`--`
40
41
42			`LIBRARY ieee;`
43			`USE ieee.std_logic_1164.all;`
44			`USE ieee.std_logic_arith.all;`
45
46			`ARCHITECTURE pipeline OF FPadd IS`
47
48			`-- Architecture declarations`
49
50			`-- Internal signal declarations`
51			`SIGNAL ADD_SUB_out : std_logic;`
52			`SIGNAL A_EXP : std_logic_vector(7 DOWNTO 0);`
53			`SIGNAL A_SIGN : std_logic;`
54			`SIGNAL A_SIGN_stage2 : std_logic;`
55			`SIGNAL A_SIGN_stage3 : std_logic;`
56			`SIGNAL A_align : std_logic_vector(28 DOWNTO 0);`
57			`SIGNAL A_in : std_logic_vector(28 DOWNTO 0);`
58			`SIGNAL A_isINF : std_logic;`
59			`SIGNAL A_isNaN : std_logic;`
60			`SIGNAL A_isZ : std_logic;`
61			`SIGNAL B_EXP : std_logic_vector(7 DOWNTO 0);`
62			`SIGNAL B_XSIGN : std_logic;`
63			`SIGNAL B_XSIGN_stage2 : std_logic;`
64			`SIGNAL B_XSIGN_stage3 : std_logic;`
65			`SIGNAL B_align : std_logic_vector(28 DOWNTO 0);`
66			`SIGNAL B_in : std_logic_vector(28 DOWNTO 0);`
67			`SIGNAL B_isINF : std_logic;`
68			`SIGNAL B_isNaN : std_logic;`
69			`SIGNAL B_isZ : std_logic;`
70			`SIGNAL EXP_base : std_logic_vector(7 DOWNTO 0);`
71			`SIGNAL EXP_base_stage2 : std_logic_vector(7 DOWNTO 0);`
72			`SIGNAL EXP_diff : std_logic_vector(8 DOWNTO 0);`
73			`SIGNAL EXP_norm : std_logic_vector(7 DOWNTO 0);`
74			`SIGNAL OV : std_logic;`
75			`SIGNAL OV_stage4 : std_logic;`
76			`SIGNAL SIG_norm : std_logic_vector(27 DOWNTO 0);`
77			`SIGNAL SIG_norm2 : std_logic_vector(27 DOWNTO 0);`
78			`SIGNAL Z_EXP : std_logic_vector(7 DOWNTO 0);`
79			`SIGNAL Z_SIGN : std_logic;`
80			`SIGNAL Z_SIGN_stage4 : std_logic;`
81			`SIGNAL add_out : std_logic_vector(28 DOWNTO 0);`
82			`SIGNAL cin : std_logic;`
83			`SIGNAL cin_sub : std_logic;`
84			`SIGNAL invert_A : std_logic;`
85			`SIGNAL invert_B : std_logic;`
86			`SIGNAL isINF_tab : std_logic;`
87			`SIGNAL isINF_tab_stage2 : std_logic;`
88			`SIGNAL isINF_tab_stage3 : std_logic;`
89			`SIGNAL isINF_tab_stage4 : std_logic;`
90			`SIGNAL isNaN : std_logic;`
91			`SIGNAL isNaN_stage2 : std_logic;`
92			`SIGNAL isNaN_stage3 : std_logic;`
93			`SIGNAL isNaN_stage4 : std_logic;`
94			`SIGNAL isZ_tab : std_logic;`
95			`SIGNAL isZ_tab_stage2 : std_logic;`
96			`SIGNAL isZ_tab_stage3 : std_logic;`
97			`SIGNAL isZ_tab_stage4 : std_logic;`
98			`SIGNAL zero : std_logic;`
99			`SIGNAL zero_stage4 : std_logic;`
100
101
102			`-- Component Declarations`
103			`COMPONENT FPadd_stage1`
104			`PORT (`
105			`ADD_SUB : IN std_logic ;`
106			`FP_A : IN std_logic_vector (31 DOWNTO 0);`
107			`FP_B : IN std_logic_vector (31 DOWNTO 0);`
108			`clk : IN std_logic ;`
109			`ADD_SUB_out : OUT std_logic ;`
110			`A_EXP : OUT std_logic_vector (7 DOWNTO 0);`
111			`A_SIGN : OUT std_logic ;`
112			`A_in : OUT std_logic_vector (28 DOWNTO 0);`
113			`A_isINF : OUT std_logic ;`
114			`A_isNaN : OUT std_logic ;`
115			`A_isZ : OUT std_logic ;`
116			`B_EXP : OUT std_logic_vector (7 DOWNTO 0);`
117			`B_XSIGN : OUT std_logic ;`
118			`B_in : OUT std_logic_vector (28 DOWNTO 0);`
119			`B_isINF : OUT std_logic ;`
120			`B_isNaN : OUT std_logic ;`
121			`B_isZ : OUT std_logic ;`
122			`EXP_diff : OUT std_logic_vector (8 DOWNTO 0);`
123			`cin_sub : OUT std_logic`
124			`);`
125			`END COMPONENT;`
126			`COMPONENT FPadd_stage2`
127			`PORT (`
128			`ADD_SUB_out : IN std_logic ;`
129			`A_EXP : IN std_logic_vector (7 DOWNTO 0);`
130			`A_SIGN : IN std_logic ;`
131			`A_in : IN std_logic_vector (28 DOWNTO 0);`
132			`A_isINF : IN std_logic ;`
133			`A_isNaN : IN std_logic ;`
134			`A_isZ : IN std_logic ;`
135			`B_EXP : IN std_logic_vector (7 DOWNTO 0);`
136			`B_XSIGN : IN std_logic ;`
137			`B_in : IN std_logic_vector (28 DOWNTO 0);`
138			`B_isINF : IN std_logic ;`
139			`B_isNaN : IN std_logic ;`
140			`B_isZ : IN std_logic ;`
141			`EXP_diff : IN std_logic_vector (8 DOWNTO 0);`
142			`cin_sub : IN std_logic ;`
143			`clk : IN std_logic ;`
144			`A_SIGN_stage2 : OUT std_logic ;`
145			`A_align : OUT std_logic_vector (28 DOWNTO 0);`
146			`B_XSIGN_stage2 : OUT std_logic ;`
147			`B_align : OUT std_logic_vector (28 DOWNTO 0);`
148			`EXP_base_stage2 : OUT std_logic_vector (7 DOWNTO 0);`
149			`cin : OUT std_logic ;`
150			`invert_A : OUT std_logic ;`
151			`invert_B : OUT std_logic ;`
152			`isINF_tab_stage2 : OUT std_logic ;`
153			`isNaN_stage2 : OUT std_logic ;`
154			`isZ_tab_stage2 : OUT std_logic`
155			`);`
156			`END COMPONENT;`
157			`COMPONENT FPadd_stage3`
158			`PORT (`
159			`A_SIGN_stage2 : IN std_logic ;`
160			`A_align : IN std_logic_vector (28 DOWNTO 0);`
161			`B_XSIGN_stage2 : IN std_logic ;`
162			`B_align : IN std_logic_vector (28 DOWNTO 0);`
163			`EXP_base_stage2 : IN std_logic_vector (7 DOWNTO 0);`
164			`cin : IN std_logic ;`
165			`clk : IN std_logic ;`
166			`invert_A : IN std_logic ;`
167			`invert_B : IN std_logic ;`
168			`isINF_tab_stage2 : IN std_logic ;`
169			`isNaN_stage2 : IN std_logic ;`
170			`isZ_tab_stage2 : IN std_logic ;`
171			`A_SIGN_stage3 : OUT std_logic ;`
172			`B_XSIGN_stage3 : OUT std_logic ;`
173			`EXP_base : OUT std_logic_vector (7 DOWNTO 0);`
174			`add_out : OUT std_logic_vector (28 DOWNTO 0);`
175			`isINF_tab_stage3 : OUT std_logic ;`
176			`isNaN_stage3 : OUT std_logic ;`
177			`isZ_tab_stage3 : OUT std_logic`
178			`);`
179			`END COMPONENT;`
180			`COMPONENT FPadd_stage4`
181			`PORT (`
182			`A_SIGN_stage3 : IN std_logic ;`
183			`B_XSIGN_stage3 : IN std_logic ;`
184			`EXP_base : IN std_logic_vector (7 DOWNTO 0);`
185			`add_out : IN std_logic_vector (28 DOWNTO 0);`
186			`clk : IN std_logic ;`
187			`isINF_tab_stage3 : IN std_logic ;`
188			`isNaN_stage3 : IN std_logic ;`
189			`isZ_tab_stage3 : IN std_logic ;`
190			`EXP_norm : OUT std_logic_vector (7 DOWNTO 0);`
191			`OV_stage4 : OUT std_logic ;`
192			`SIG_norm : OUT std_logic_vector (27 DOWNTO 0);`
193			`Z_SIGN_stage4 : OUT std_logic ;`
194			`isINF_tab_stage4 : OUT std_logic ;`
195			`isNaN_stage4 : OUT std_logic ;`
196			`isZ_tab_stage4 : OUT std_logic ;`
197			`zero_stage4 : OUT std_logic`
198			`);`
199			`END COMPONENT;`
200			`COMPONENT FPadd_stage5`
201			`PORT (`
202			`EXP_norm : IN std_logic_vector (7 DOWNTO 0);`
203			`OV_stage4 : IN std_logic ;`
204			`SIG_norm : IN std_logic_vector (27 DOWNTO 0);`
205			`Z_SIGN_stage4 : IN std_logic ;`
206			`clk : IN std_logic ;`
207			`isINF_tab_stage4 : IN std_logic ;`
208			`isNaN_stage4 : IN std_logic ;`
209			`isZ_tab_stage4 : IN std_logic ;`
210			`zero_stage4 : IN std_logic ;`
211			`OV : OUT std_logic ;`
212			`SIG_norm2 : OUT std_logic_vector (27 DOWNTO 0);`
213			`Z_EXP : OUT std_logic_vector (7 DOWNTO 0);`
214			`Z_SIGN : OUT std_logic ;`
215			`isINF_tab : OUT std_logic ;`
216			`isNaN : OUT std_logic ;`
217			`isZ_tab : OUT std_logic ;`
218			`zero : OUT std_logic`
219			`);`
220			`END COMPONENT;`
221			`COMPONENT FPadd_stage6`
222			`PORT (`
223			`OV : IN std_logic ;`
224			`SIG_norm2 : IN std_logic_vector (27 DOWNTO 0);`
225			`Z_EXP : IN std_logic_vector (7 DOWNTO 0);`
226			`Z_SIGN : IN std_logic ;`
227			`clk : IN std_logic ;`
228			`isINF_tab : IN std_logic ;`
229			`isNaN : IN std_logic ;`
230			`isZ_tab : IN std_logic ;`
231			`zero : IN std_logic ;`
232			`FP_Z : OUT std_logic_vector (31 DOWNTO 0)`
233			`);`
234			`END COMPONENT;`
235
236			`-- Optional embedded configurations`
237			`-- pragma synthesis_off`
238	4	gmarcus	`FOR ALL : FPadd_stage1 USE ENTITY work.FPadd_stage1;`
239			`FOR ALL : FPadd_stage2 USE ENTITY work.FPadd_stage2;`
240			`FOR ALL : FPadd_stage3 USE ENTITY work.FPadd_stage3;`
241			`FOR ALL : FPadd_stage4 USE ENTITY work.FPadd_stage4;`
242			`FOR ALL : FPadd_stage5 USE ENTITY work.FPadd_stage5;`
243			`FOR ALL : FPadd_stage6 USE ENTITY work.FPadd_stage6;`
244	3	gmarcus	`-- pragma synthesis_on`
245
246
247			`BEGIN`
248
249			`-- Instance port mappings.`
250			`I1 : FPadd_stage1`
251			`PORT MAP (`
252			`ADD_SUB => ADD_SUB,`
253			`FP_A => FP_A,`
254			`FP_B => FP_B,`
255			`clk => clk,`
256			`ADD_SUB_out => ADD_SUB_out,`
257			`A_EXP => A_EXP,`
258			`A_SIGN => A_SIGN,`
259			`A_in => A_in,`
260			`A_isINF => A_isINF,`
261			`A_isNaN => A_isNaN,`
262			`A_isZ => A_isZ,`
263			`B_EXP => B_EXP,`
264			`B_XSIGN => B_XSIGN,`
265			`B_in => B_in,`
266			`B_isINF => B_isINF,`
267			`B_isNaN => B_isNaN,`
268			`B_isZ => B_isZ,`
269			`EXP_diff => EXP_diff,`
270			`cin_sub => cin_sub`
271			`);`
272			`I2 : FPadd_stage2`
273			`PORT MAP (`
274			`ADD_SUB_out => ADD_SUB_out,`
275			`A_EXP => A_EXP,`
276			`A_SIGN => A_SIGN,`
277			`A_in => A_in,`
278			`A_isINF => A_isINF,`
279			`A_isNaN => A_isNaN,`
280			`A_isZ => A_isZ,`
281			`B_EXP => B_EXP,`
282			`B_XSIGN => B_XSIGN,`
283			`B_in => B_in,`
284			`B_isINF => B_isINF,`
285			`B_isNaN => B_isNaN,`
286			`B_isZ => B_isZ,`
287			`EXP_diff => EXP_diff,`
288			`cin_sub => cin_sub,`
289			`clk => clk,`
290			`A_SIGN_stage2 => A_SIGN_stage2,`
291			`A_align => A_align,`
292			`B_XSIGN_stage2 => B_XSIGN_stage2,`
293			`B_align => B_align,`
294			`EXP_base_stage2 => EXP_base_stage2,`
295			`cin => cin,`
296			`invert_A => invert_A,`
297			`invert_B => invert_B,`
298			`isINF_tab_stage2 => isINF_tab_stage2,`
299			`isNaN_stage2 => isNaN_stage2,`
300			`isZ_tab_stage2 => isZ_tab_stage2`
301			`);`
302			`I3 : FPadd_stage3`
303			`PORT MAP (`
304			`A_SIGN_stage2 => A_SIGN_stage2,`
305			`A_align => A_align,`
306			`B_XSIGN_stage2 => B_XSIGN_stage2,`
307			`B_align => B_align,`
308			`EXP_base_stage2 => EXP_base_stage2,`
309			`cin => cin,`
310			`clk => clk,`
311			`invert_A => invert_A,`
312			`invert_B => invert_B,`
313			`isINF_tab_stage2 => isINF_tab_stage2,`
314			`isNaN_stage2 => isNaN_stage2,`
315			`isZ_tab_stage2 => isZ_tab_stage2,`
316			`A_SIGN_stage3 => A_SIGN_stage3,`
317			`B_XSIGN_stage3 => B_XSIGN_stage3,`
318			`EXP_base => EXP_base,`
319			`add_out => add_out,`
320			`isINF_tab_stage3 => isINF_tab_stage3,`
321			`isNaN_stage3 => isNaN_stage3,`
322			`isZ_tab_stage3 => isZ_tab_stage3`
323			`);`
324			`I4 : FPadd_stage4`
325			`PORT MAP (`
326			`A_SIGN_stage3 => A_SIGN_stage3,`
327			`B_XSIGN_stage3 => B_XSIGN_stage3,`
328			`EXP_base => EXP_base,`
329			`add_out => add_out,`
330			`clk => clk,`
331			`isINF_tab_stage3 => isINF_tab_stage3,`
332			`isNaN_stage3 => isNaN_stage3,`
333			`isZ_tab_stage3 => isZ_tab_stage3,`
334			`EXP_norm => EXP_norm,`
335			`OV_stage4 => OV_stage4,`
336			`SIG_norm => SIG_norm,`
337			`Z_SIGN_stage4 => Z_SIGN_stage4,`
338			`isINF_tab_stage4 => isINF_tab_stage4,`
339			`isNaN_stage4 => isNaN_stage4,`
340			`isZ_tab_stage4 => isZ_tab_stage4,`
341			`zero_stage4 => zero_stage4`
342			`);`
343			`I5 : FPadd_stage5`
344			`PORT MAP (`
345			`EXP_norm => EXP_norm,`
346			`OV_stage4 => OV_stage4,`
347			`SIG_norm => SIG_norm,`
348			`Z_SIGN_stage4 => Z_SIGN_stage4,`
349			`clk => clk,`
350			`isINF_tab_stage4 => isINF_tab_stage4,`
351			`isNaN_stage4 => isNaN_stage4,`
352			`isZ_tab_stage4 => isZ_tab_stage4,`
353			`zero_stage4 => zero_stage4,`
354			`OV => OV,`
355			`SIG_norm2 => SIG_norm2,`
356			`Z_EXP => Z_EXP,`
357			`Z_SIGN => Z_SIGN,`
358			`isINF_tab => isINF_tab,`
359			`isNaN => isNaN,`
360			`isZ_tab => isZ_tab,`
361			`zero => zero`
362			`);`
363			`I6 : FPadd_stage6`
364			`PORT MAP (`
365			`OV => OV,`
366			`SIG_norm2 => SIG_norm2,`
367			`Z_EXP => Z_EXP,`
368			`Z_SIGN => Z_SIGN,`
369			`clk => clk,`
370			`isINF_tab => isINF_tab,`
371			`isNaN => isNaN,`
372			`isZ_tab => isZ_tab,`
373			`zero => zero,`
374			`FP_Z => FP_Z`
375			`);`
376
377			`END pipeline;`