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[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [adder/] [fpadd_single_cycle.vhd] - Blame information for rev 5

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Line No. Rev Author Line
1 4 gmarcus
-- VHDL Entity work.FPadd.symbol
2 3 gmarcus
--
3
-- Created by
4
-- Guillermo Marcus, gmarcus@ieee.org
5
-- using Mentor Graphics FPGA Advantage tools.
6
--
7
-- Visit "http://fpga.mty.itesm.mx" for more info.
8
--
9
-- 2003-2004. V1.0
10
--
11
 
12
LIBRARY ieee;
13
USE ieee.std_logic_1164.all;
14
USE ieee.std_logic_arith.all;
15
 
16
ENTITY FPadd IS
17
   PORT(
18
      ADD_SUB : IN     std_logic;
19
      FP_A    : IN     std_logic_vector (31 DOWNTO 0);
20
      FP_B    : IN     std_logic_vector (31 DOWNTO 0);
21
      clk     : IN     std_logic;
22
      FP_Z    : OUT    std_logic_vector (31 DOWNTO 0)
23
   );
24
 
25
-- Declarations
26
 
27
END FPadd ;
28
 
29
--
30 4 gmarcus
-- VHDL Architecture work.FPadd.single_cycle
31 3 gmarcus
--
32
-- Created by
33
-- Guillermo Marcus, gmarcus@ieee.org
34
-- using Mentor Graphics FPGA Advantage tools.
35
--
36
-- Visit "http://fpga.mty.itesm.mx" for more info.
37
--
38
-- Copyright 2003-2004. V1.0
39
--
40
 
41
 
42
LIBRARY ieee;
43
USE ieee.std_logic_1164.all;
44
USE ieee.std_logic_arith.all;
45
 
46
ARCHITECTURE single_cycle OF FPadd IS
47
 
48
   -- Architecture declarations
49
      -- Non hierarchical truthtable declarations
50
 
51
 
52
      -- Non hierarchical truthtable declarations
53
 
54
 
55
      -- Non hierarchical truthtable declarations
56
 
57
 
58
 
59
   -- Internal signal declarations
60
   SIGNAL A_CS      : std_logic_vector(28 DOWNTO 0);
61
   SIGNAL A_EXP     : std_logic_vector(7 DOWNTO 0);
62
   SIGNAL A_SIG     : std_logic_vector(31 DOWNTO 0);
63
   SIGNAL A_SIGN    : std_logic;
64
   SIGNAL A_in      : std_logic_vector(28 DOWNTO 0);
65
   SIGNAL A_isDN    : std_logic;
66
   SIGNAL A_isINF   : std_logic;
67
   SIGNAL A_isNaN   : std_logic;
68
   SIGNAL A_isZ     : std_logic;
69
   SIGNAL B_CS      : std_logic_vector(28 DOWNTO 0);
70
   SIGNAL B_EXP     : std_logic_vector(7 DOWNTO 0);
71
   SIGNAL B_SIG     : std_logic_vector(31 DOWNTO 0);
72
   SIGNAL B_SIGN    : std_logic;
73
   SIGNAL B_XSIGN   : std_logic;
74
   SIGNAL B_in      : std_logic_vector(28 DOWNTO 0);
75
   SIGNAL B_isDN    : std_logic;
76
   SIGNAL B_isINF   : std_logic;
77
   SIGNAL B_isNaN   : std_logic;
78
   SIGNAL B_isZ     : std_logic;
79
   SIGNAL EXP_base  : std_logic_vector(7 DOWNTO 0);
80
   SIGNAL EXP_diff  : std_logic_vector(8 DOWNTO 0);
81
   SIGNAL EXP_isINF : std_logic;
82
   SIGNAL EXP_norm  : std_logic_vector(7 DOWNTO 0);
83
   SIGNAL EXP_round : std_logic_vector(7 DOWNTO 0);
84
   SIGNAL EXP_selC  : std_logic_vector(7 DOWNTO 0);
85
   SIGNAL OV        : std_logic;
86
   SIGNAL SIG_norm  : std_logic_vector(27 DOWNTO 0);
87
   SIGNAL SIG_norm2 : std_logic_vector(27 DOWNTO 0);
88
   SIGNAL SIG_round : std_logic_vector(27 DOWNTO 0);
89
   SIGNAL SIG_selC  : std_logic_vector(27 DOWNTO 0);
90
   SIGNAL Z_EXP     : std_logic_vector(7 DOWNTO 0);
91
   SIGNAL Z_SIG     : std_logic_vector(22 DOWNTO 0);
92
   SIGNAL Z_SIGN    : std_logic;
93
   SIGNAL a_align   : std_logic_vector(28 DOWNTO 0);
94
   SIGNAL a_exp_in  : std_logic_vector(8 DOWNTO 0);
95
   SIGNAL a_inv     : std_logic_vector(28 DOWNTO 0);
96
   SIGNAL add_out   : std_logic_vector(28 DOWNTO 0);
97
   SIGNAL b_align   : std_logic_vector(28 DOWNTO 0);
98
   SIGNAL b_exp_in  : std_logic_vector(8 DOWNTO 0);
99
   SIGNAL b_inv     : std_logic_vector(28 DOWNTO 0);
100
   SIGNAL cin       : std_logic;
101
   SIGNAL cin_sub   : std_logic;
102
   SIGNAL invert_A  : std_logic;
103
   SIGNAL invert_B  : std_logic;
104
   SIGNAL isINF     : std_logic;
105
   SIGNAL isINF_tab : std_logic;
106
   SIGNAL isNaN     : std_logic;
107
   SIGNAL isZ       : std_logic;
108
   SIGNAL isZ_tab   : std_logic;
109
   SIGNAL mux_sel   : std_logic;
110
   SIGNAL zero      : std_logic;
111
 
112
 
113
   -- ModuleWare signal declarations(v1.1) for instance 'I13' of 'mux'
114
   SIGNAL mw_I13din0 : std_logic_vector(7 DOWNTO 0);
115
   SIGNAL mw_I13din1 : std_logic_vector(7 DOWNTO 0);
116
 
117
   -- Component Declarations
118
   COMPONENT FPadd_normalize
119
   PORT (
120
      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
121
      SIG_in  : IN     std_logic_vector (27 DOWNTO 0);
122
      EXP_out : OUT    std_logic_vector (7 DOWNTO 0);
123
      SIG_out : OUT    std_logic_vector (27 DOWNTO 0);
124
      zero    : OUT    std_logic
125
   );
126
   END COMPONENT;
127
   COMPONENT FPalign
128
   PORT (
129
      A_in  : IN     std_logic_vector (28 DOWNTO 0);
130
      B_in  : IN     std_logic_vector (28 DOWNTO 0);
131
      cin   : IN     std_logic ;
132
      diff  : IN     std_logic_vector (8 DOWNTO 0);
133
      A_out : OUT    std_logic_vector (28 DOWNTO 0);
134
      B_out : OUT    std_logic_vector (28 DOWNTO 0)
135
   );
136
   END COMPONENT;
137
   COMPONENT FPinvert
138
   GENERIC (
139
      width : integer := 29
140
   );
141
   PORT (
142
      A_in     : IN     std_logic_vector (width-1 DOWNTO 0);
143
      B_in     : IN     std_logic_vector (width-1 DOWNTO 0);
144
      invert_A : IN     std_logic ;
145
      invert_B : IN     std_logic ;
146
      A_out    : OUT    std_logic_vector (width-1 DOWNTO 0);
147
      B_out    : OUT    std_logic_vector (width-1 DOWNTO 0)
148
   );
149
   END COMPONENT;
150
   COMPONENT FPnormalize
151
   GENERIC (
152
      SIG_width : integer := 28
153
   );
154
   PORT (
155
      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);
156
      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
157
      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
158
      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
159
   );
160
   END COMPONENT;
161
   COMPONENT FPround
162
   GENERIC (
163
      SIG_width : integer := 28
164
   );
165
   PORT (
166
      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);
167
      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
168
      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
169
      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
170
   );
171
   END COMPONENT;
172
   COMPONENT FPselComplement
173
   GENERIC (
174
      SIG_width : integer := 28
175
   );
176
   PORT (
177
      SIG_in  : IN     std_logic_vector (SIG_width DOWNTO 0);
178
      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
179
      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
180
      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
181
   );
182
   END COMPONENT;
183
   COMPONENT FPswap
184
   GENERIC (
185
      width : integer := 29
186
   );
187
   PORT (
188
      A_in    : IN     std_logic_vector (width-1 DOWNTO 0);
189
      B_in    : IN     std_logic_vector (width-1 DOWNTO 0);
190
      swap_AB : IN     std_logic ;
191
      A_out   : OUT    std_logic_vector (width-1 DOWNTO 0);
192
      B_out   : OUT    std_logic_vector (width-1 DOWNTO 0)
193
   );
194
   END COMPONENT;
195
   COMPONENT PackFP
196
   PORT (
197
      SIGN  : IN     std_logic ;
198
      EXP   : IN     std_logic_vector (7 DOWNTO 0);
199
      SIG   : IN     std_logic_vector (22 DOWNTO 0);
200
      isNaN : IN     std_logic ;
201
      isINF : IN     std_logic ;
202
      isZ   : IN     std_logic ;
203
      FP    : OUT    std_logic_vector (31 DOWNTO 0)
204
   );
205
   END COMPONENT;
206
   COMPONENT UnpackFP
207
   PORT (
208
      FP    : IN     std_logic_vector (31 DOWNTO 0);
209
      SIG   : OUT    std_logic_vector (31 DOWNTO 0);
210
      EXP   : OUT    std_logic_vector (7 DOWNTO 0);
211
      SIGN  : OUT    std_logic ;
212
      isNaN : OUT    std_logic ;
213
      isINF : OUT    std_logic ;
214
      isZ   : OUT    std_logic ;
215
      isDN  : OUT    std_logic
216
   );
217
   END COMPONENT;
218
 
219
   -- Optional embedded configurations
220
   -- pragma synthesis_off
221 4 gmarcus
   FOR ALL : FPadd_normalize USE ENTITY work.FPadd_normalize;
222
   FOR ALL : FPalign USE ENTITY work.FPalign;
223
   FOR ALL : FPinvert USE ENTITY work.FPinvert;
224
   FOR ALL : FPnormalize USE ENTITY work.FPnormalize;
225
   FOR ALL : FPround USE ENTITY work.FPround;
226
   FOR ALL : FPselComplement USE ENTITY work.FPselComplement;
227
   FOR ALL : FPswap USE ENTITY work.FPswap;
228
   FOR ALL : PackFP USE ENTITY work.PackFP;
229
   FOR ALL : UnpackFP USE ENTITY work.UnpackFP;
230 3 gmarcus
   -- pragma synthesis_on
231
 
232
 
233
BEGIN
234
   -- Architecture concurrent statements
235
   -- HDL Embedded Text Block 1 eb1
236
   -- eb1 1
237
   cin_sub <= (A_isDN OR A_isZ) XOR
238
   (B_isDN OR B_isZ);
239
 
240
   -- HDL Embedded Text Block 2 eb2
241
   -- eb2 2
242
   Z_SIG <= SIG_norm2(25 DOWNTO 3);
243
 
244
   -- HDL Embedded Block 3 eb3
245
   -- Non hierarchical truthtable
246
   ---------------------------------------------------------------------------
247
   eb3_truth_process: PROCESS(ADD_SUB, A_isINF, A_isNaN, A_isZ, B_isINF, B_isNaN, B_isZ)
248
   ---------------------------------------------------------------------------
249
   BEGIN
250
      -- Block 1
251
      IF (A_isNaN = '1') THEN
252
         isINF_tab <= '0';
253
         isNaN <= '1';
254
         isZ_tab <= '0';
255
      ELSIF (B_isNaN = '1') THEN
256
         isINF_tab <= '0';
257
         isNaN <= '1';
258
         isZ_tab <= '0';
259
      ELSIF (ADD_SUB = '1') AND (A_isINF = '1') AND (B_isINF = '1') THEN
260
         isINF_tab <= '1';
261
         isNaN <= '0';
262
         isZ_tab <= '0';
263
      ELSIF (ADD_SUB = '0') AND (A_isINF = '1') AND (B_isINF = '1') THEN
264
         isINF_tab <= '0';
265
         isNaN <= '1';
266
         isZ_tab <= '0';
267
      ELSIF (A_isINF = '1') THEN
268
         isINF_tab <= '1';
269
         isNaN <= '0';
270
         isZ_tab <= '0';
271
      ELSIF (B_isINF = '1') THEN
272
         isINF_tab <= '1';
273
         isNaN <= '0';
274
         isZ_tab <= '0';
275
      ELSIF (A_isZ = '1') AND (B_isZ = '1') THEN
276
         isINF_tab <= '0';
277
         isNaN <= '0';
278
         isZ_tab <= '1';
279
      ELSE
280
         isINF_tab <= '0';
281
         isNaN <= '0';
282
         isZ_tab <= '0';
283
      END IF;
284
 
285
   END PROCESS eb3_truth_process;
286
 
287
   -- Architecture concurrent statements
288
 
289
 
290
 
291
   -- HDL Embedded Text Block 4 eb4
292
   -- eb4 4 
293
   mux_sel <= EXP_diff(8);
294
 
295
   -- HDL Embedded Block 5 InvertLogic
296
   -- Non hierarchical truthtable
297
   ---------------------------------------------------------------------------
298
   InvertLogic_truth_process: PROCESS(A_SIGN, B_XSIGN, EXP_diff)
299
   ---------------------------------------------------------------------------
300
   BEGIN
301
      -- Block 1
302
      IF (A_SIGN = '0') AND (B_XSIGN = '0') THEN
303
         invert_A <= '0';
304
         invert_B <= '0';
305
      ELSIF (A_SIGN = '1') AND (B_XSIGN = '1') THEN
306
         invert_A <= '0';
307
         invert_B <= '0';
308
      ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (EXP_diff(8) = '0') THEN
309
         invert_A <= '0';
310
         invert_B <= '1';
311
      ELSIF (A_SIGN = '0') AND (B_XSIGN = '1') AND (EXP_diff(8) = '1') THEN
312
         invert_A <= '1';
313
         invert_B <= '0';
314
      ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (EXP_diff(8) = '0') THEN
315
         invert_A <= '1';
316
         invert_B <= '0';
317
      ELSIF (A_SIGN = '1') AND (B_XSIGN = '0') AND (EXP_diff(8) = '1') THEN
318
         invert_A <= '0';
319
         invert_B <= '1';
320
      ELSE
321
         invert_A <= '0';
322
         invert_B <= '0';
323
      END IF;
324
 
325
   END PROCESS InvertLogic_truth_process;
326
 
327
   -- Architecture concurrent statements
328
 
329
 
330
 
331
   -- HDL Embedded Block 6 SignLogic
332
   -- Non hierarchical truthtable
333
   ---------------------------------------------------------------------------
334
   SignLogic_truth_process: PROCESS(A_SIGN, B_XSIGN, add_out)
335
   ---------------------------------------------------------------------------
336
      VARIABLE b1_A_SIGNB_XSIGNadd_out_28 : std_logic_vector(2 DOWNTO 0);
337
   BEGIN
338
      -- Block 1
339
      b1_A_SIGNB_XSIGNadd_out_28 := A_SIGN & B_XSIGN & add_out(28);
340
 
341
      CASE b1_A_SIGNB_XSIGNadd_out_28 IS
342
      WHEN "000" =>
343
         OV <= '0';
344
         Z_SIGN <= '0';
345
      WHEN "001" =>
346
         OV <= '1';
347
         Z_SIGN <= '0';
348
      WHEN "010" =>
349
         OV <= '0';
350
         Z_SIGN <= '0';
351
      WHEN "011" =>
352
         OV <= '0';
353
         Z_SIGN <= '1';
354
      WHEN "100" =>
355
         OV <= '0';
356
         Z_SIGN <= '0';
357
      WHEN "101" =>
358
         OV <= '0';
359
         Z_SIGN <= '1';
360
      WHEN "110" =>
361
         OV <= '0';
362
         Z_SIGN <= '1';
363
      WHEN "111" =>
364
         OV <= '1';
365
         Z_SIGN <= '1';
366
      WHEN OTHERS =>
367
         OV <= '0';
368
         Z_SIGN <= '0';
369
      END CASE;
370
 
371
   END PROCESS SignLogic_truth_process;
372
 
373
   -- Architecture concurrent statements
374
 
375
 
376
 
377
   -- HDL Embedded Text Block 7 eb5
378
   -- eb5 7 
379
   A_in <= "00" & A_SIG(23 DOWNTO 0) & "000";
380
 
381
   -- HDL Embedded Text Block 8 eb6
382
   -- eb6 8                      
383
   B_in <= "00" & B_SIG(23 DOWNTO 0) & "000";
384
 
385
   -- HDL Embedded Text Block 9 eb7
386
   -- eb7 9
387
   EXP_isINF <= '1' WHEN (OV='1' OR Z_EXP=X"FF") ELSE '0';
388
 
389
   -- HDL Embedded Text Block 10 eb8
390
   -- eb8 10
391
   a_exp_in <= "0" & A_EXP;
392
 
393
   -- HDL Embedded Text Block 11 eb9
394
   -- eb9 11
395
   b_exp_in <= "0" & B_EXP;
396
 
397
 
398
   -- ModuleWare code(v1.1) for instance 'I4' of 'add'
399
   I4combo: PROCESS (a_inv, b_inv, cin)
400
   VARIABLE mw_I4t0 : std_logic_vector(29 DOWNTO 0);
401
   VARIABLE mw_I4t1 : std_logic_vector(29 DOWNTO 0);
402
   VARIABLE mw_I4sum : signed(29 DOWNTO 0);
403
   VARIABLE mw_I4carry : std_logic;
404
   BEGIN
405
      mw_I4t0 := a_inv(28) & a_inv;
406
      mw_I4t1 := b_inv(28) & b_inv;
407
      mw_I4carry := cin;
408
      mw_I4sum := signed(mw_I4t0) + signed(mw_I4t1) + mw_I4carry;
409
      add_out <= conv_std_logic_vector(mw_I4sum(28 DOWNTO 0),29);
410
   END PROCESS I4combo;
411
 
412
   -- ModuleWare code(v1.1) for instance 'I13' of 'mux'
413
   I13combo: PROCESS(mw_I13din0, mw_I13din1, mux_sel)
414
   VARIABLE dtemp : std_logic_vector(7 DOWNTO 0);
415
   BEGIN
416
      CASE mux_sel IS
417
      WHEN '0'|'L' => dtemp := mw_I13din0;
418
      WHEN '1'|'H' => dtemp := mw_I13din1;
419
      WHEN OTHERS => dtemp := (OTHERS => 'X');
420
      END CASE;
421
      EXP_base <= dtemp;
422
   END PROCESS I13combo;
423
   mw_I13din0 <= A_EXP;
424
   mw_I13din1 <= B_EXP;
425
 
426
   -- ModuleWare code(v1.1) for instance 'I7' of 'or'
427
   isINF <= EXP_isINF OR isINF_tab;
428
 
429
   -- ModuleWare code(v1.1) for instance 'I15' of 'or'
430
   cin <= invert_B OR invert_A;
431
 
432
   -- ModuleWare code(v1.1) for instance 'I17' of 'or'
433
   isZ <= zero OR isZ_tab;
434
 
435
   -- ModuleWare code(v1.1) for instance 'I3' of 'sub'
436
   I3combo: PROCESS (a_exp_in, b_exp_in, cin_sub)
437
   VARIABLE mw_I3t0 : std_logic_vector(9 DOWNTO 0);
438
   VARIABLE mw_I3t1 : std_logic_vector(9 DOWNTO 0);
439
   VARIABLE diff : signed(9 DOWNTO 0);
440
   VARIABLE borrow : std_logic;
441
   BEGIN
442
      mw_I3t0 := a_exp_in(8) & a_exp_in;
443
      mw_I3t1 := b_exp_in(8) & b_exp_in;
444
      borrow := cin_sub;
445
      diff := signed(mw_I3t0) - signed(mw_I3t1) - borrow;
446
      EXP_diff <= conv_std_logic_vector(diff(8 DOWNTO 0),9);
447
   END PROCESS I3combo;
448
 
449
   -- ModuleWare code(v1.1) for instance 'I16' of 'xnor'
450
   B_XSIGN <= NOT(B_SIGN XOR ADD_SUB);
451
 
452
   -- Instance port mappings.
453
   I8 : FPadd_normalize
454
      PORT MAP (
455
         EXP_in  => EXP_selC,
456
         SIG_in  => SIG_selC,
457
         EXP_out => EXP_norm,
458
         SIG_out => SIG_norm,
459
         zero    => zero
460
      );
461
   I6 : FPalign
462
      PORT MAP (
463
         A_in  => A_CS,
464
         B_in  => B_CS,
465
         cin   => cin_sub,
466
         diff  => EXP_diff,
467
         A_out => a_align,
468
         B_out => b_align
469
      );
470
   I14 : FPinvert
471
      GENERIC MAP (
472
         width => 29
473
      )
474
      PORT MAP (
475
         A_in     => a_align,
476
         B_in     => b_align,
477
         invert_A => invert_A,
478
         invert_B => invert_B,
479
         A_out    => a_inv,
480
         B_out    => b_inv
481
      );
482
   I11 : FPnormalize
483
      GENERIC MAP (
484
         SIG_width => 28
485
      )
486
      PORT MAP (
487
         SIG_in  => SIG_round,
488
         EXP_in  => EXP_round,
489
         SIG_out => SIG_norm2,
490
         EXP_out => Z_EXP
491
      );
492
   I10 : FPround
493
      GENERIC MAP (
494
         SIG_width => 28
495
      )
496
      PORT MAP (
497
         SIG_in  => SIG_norm,
498
         EXP_in  => EXP_norm,
499
         SIG_out => SIG_round,
500
         EXP_out => EXP_round
501
      );
502
   I12 : FPselComplement
503
      GENERIC MAP (
504
         SIG_width => 28
505
      )
506
      PORT MAP (
507
         SIG_in  => add_out,
508
         EXP_in  => EXP_base,
509
         SIG_out => SIG_selC,
510
         EXP_out => EXP_selC
511
      );
512
   I5 : FPswap
513
      GENERIC MAP (
514
         width => 29
515
      )
516
      PORT MAP (
517
         A_in    => A_in,
518
         B_in    => B_in,
519
         swap_AB => EXP_diff(8),
520
         A_out   => A_CS,
521
         B_out   => B_CS
522
      );
523
   I2 : PackFP
524
      PORT MAP (
525
         SIGN  => Z_SIGN,
526
         EXP   => Z_EXP,
527
         SIG   => Z_SIG,
528
         isNaN => isNaN,
529
         isINF => isINF,
530
         isZ   => isZ,
531
         FP    => FP_Z
532
      );
533
   I0 : UnpackFP
534
      PORT MAP (
535
         FP    => FP_A,
536
         SIG   => A_SIG,
537
         EXP   => A_EXP,
538
         SIGN  => A_SIGN,
539
         isNaN => A_isNaN,
540
         isINF => A_isINF,
541
         isZ   => A_isZ,
542
         isDN  => A_isDN
543
      );
544
   I1 : UnpackFP
545
      PORT MAP (
546
         FP    => FP_B,
547
         SIG   => B_SIG,
548
         EXP   => B_EXP,
549
         SIGN  => B_SIGN,
550
         isNaN => B_isNaN,
551
         isINF => B_isINF,
552
         isZ   => B_isZ,
553
         isDN  => B_isDN
554
      );
555
 
556
END single_cycle;

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