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[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [adder/] [fpalign_struct.vhd] - Blame information for rev 5

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1 3 gmarcus
-- VHDL Entity HAVOC.FPalign.symbol
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--
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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-- 2003-2004. V1.0
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPalign IS
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   PORT(
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      A_in  : IN     std_logic_vector (28 DOWNTO 0);
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      B_in  : IN     std_logic_vector (28 DOWNTO 0);
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      cin   : IN     std_logic;
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      diff  : IN     std_logic_vector (8 DOWNTO 0);
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      A_out : OUT    std_logic_vector (28 DOWNTO 0);
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      B_out : OUT    std_logic_vector (28 DOWNTO 0)
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   );
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-- Declarations
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END FPalign ;
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--
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-- VHDL Architecture HAVOC.FPalign.struct
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--
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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-- Copyright 2003-2004. V1.0
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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ARCHITECTURE struct OF FPalign IS
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   -- Architecture declarations
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   -- Internal signal declarations
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   SIGNAL B_shift  : std_logic_vector(28 DOWNTO 0);
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   SIGNAL diff_int : std_logic_vector(8 DOWNTO 0);
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   SIGNAL shift_B  : std_logic_vector(5 DOWNTO 0);
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BEGIN
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   -- Architecture concurrent statements
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   -- HDL Embedded Text Block 1 eb1
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   -- eb1 1
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   PROCESS(diff_int, B_shift)
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   BEGIN
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      IF (diff_int(8)='1') THEN
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         IF (((NOT diff_int) + 1) > 28) THEN
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             B_out <= (OTHERS => '0');
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          ELSE
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              B_out <= B_shift;
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          END IF;
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      ELSE
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          IF (diff_int > 28) THEN
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             B_out <= (OTHERS => '0');
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          ELSE
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              B_out <= B_shift;
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          END IF;
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       END IF;
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   END PROCESS;
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   -- HDL Embedded Text Block 2 eb2
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   -- eb2 2   
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   PROCESS(diff_int)
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   BEGIN
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      IF (diff_int(8)='1') THEN
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            shift_B <= (NOT diff_int(5 DOWNTO 0)) + 1;
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      ELSE
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            shift_B <= diff_int(5 DOWNTO 0) ;
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      END IF;
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   END PROCESS;
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   -- HDL Embedded Text Block 3 eb3
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   -- eb3 3
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   PROCESS(cin,diff)
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   BEGIN
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      IF ((cin='1') AND (diff(8)='1')) THEN
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         diff_int <= diff + 2;
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      ELSE
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         diff_int <= diff;
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      END IF;
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   END PROCESS;
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   -- ModuleWare code(v1.1) for instance 'I0' of 'assignment'
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   A_out <= A_in;
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   -- ModuleWare code(v1.1) for instance 'I1' of 'rshift'
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   I1combo : PROCESS (B_in, shift_B)
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   VARIABLE stemp : std_logic_vector (5 DOWNTO 0);
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   VARIABLE dtemp : std_logic_vector (28 DOWNTO 0);
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   VARIABLE temp : std_logic_vector (28 DOWNTO 0);
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   BEGIN
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      temp := (OTHERS=> 'X');
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      stemp := shift_B;
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      temp := B_in;
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      FOR i IN 5 DOWNTO 0 LOOP
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         IF (i < 5) THEN
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            IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
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               dtemp := (OTHERS => '0');
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               dtemp(28 - 2**i DOWNTO 0) := temp(28 DOWNTO 2**i);
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            ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
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               dtemp := temp;
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            ELSE
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               dtemp := (OTHERS => 'X');
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            END IF;
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         ELSE
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            IF (stemp(i) = '1' OR stemp(i) = 'H') THEN
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               dtemp := (OTHERS => '0');
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            ELSIF (stemp(i) = '0' OR stemp(i) = 'L') THEN
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               dtemp := temp;
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            ELSE
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               dtemp := (OTHERS => 'X');
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            END IF;
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         END IF;
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         temp := dtemp;
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      END LOOP;
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      B_shift <= dtemp;
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   END PROCESS I1combo;
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   -- Instance port mappings.
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END struct;

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