OpenCores
URL https://opencores.org/ocsvn/fpuvhdl/fpuvhdl/trunk

Subversion Repositories fpuvhdl

[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [adder/] [fpinvert_fpinvert.vhd] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 gmarcus
--
2
-- VHDL Architecture HAVOC.FPinvert.FPinvert
3
--
4
-- Created:
5
--          by - Guillermo
6
--          at - ITESM, 20:19:07 07/19/03
7
--
8
-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
9
--
10
-- hds interface_start
11
LIBRARY ieee;
12
USE ieee.std_logic_1164.all;
13
USE ieee.std_logic_arith.all;
14
 
15
 
16
ENTITY FPinvert IS
17
   GENERIC(
18
      width : integer := 29
19
   );
20
   PORT(
21
      A_in     : IN     std_logic_vector (width-1 DOWNTO 0);
22
      B_in     : IN     std_logic_vector (width-1 DOWNTO 0);
23
      invert_A : IN     std_logic;
24
      invert_B : IN     std_logic;
25
      A_out    : OUT    std_logic_vector (width-1 DOWNTO 0);
26
      B_out    : OUT    std_logic_vector (width-1 DOWNTO 0)
27
   );
28
 
29
-- Declarations
30
 
31
END FPinvert ;
32
 
33
 
34
-- hds interface_end
35
ARCHITECTURE FPinvert OF FPinvert IS
36
BEGIN
37
 
38
A_out <= (NOT A_in) WHEN (invert_A='1') ELSE A_in;
39
 
40
B_out <= (NOT B_in) WHEN (invert_B='1') ELSE B_in;
41
 
42
END FPinvert;
43
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.