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[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [common/] [fpround_fpround.vhd] - Blame information for rev 8

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Line No. Rev Author Line
1 3 gmarcus
--
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-- VHDL Architecture HAVOC.FPround.FPround
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--
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-- Created:
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--          by - Guillermo
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--          at - ITESM, 11:08:16 07/16/03
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
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--
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-- hds interface_start
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY FPround IS
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   GENERIC(
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      SIG_width : integer := 28
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   );
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   PORT(
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      SIG_in  : IN     std_logic_vector (SIG_width-1 DOWNTO 0);
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      EXP_in  : IN     std_logic_vector (7 DOWNTO 0);
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      SIG_out : OUT    std_logic_vector (SIG_width-1 DOWNTO 0);
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      EXP_out : OUT    std_logic_vector (7 DOWNTO 0)
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   );
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-- Declarations
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END FPround ;
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-- hds interface_end
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ARCHITECTURE FPround OF FPround IS
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BEGIN
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        EXP_out <= EXP_in;
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PROCESS(SIG_in)
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BEGIN
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--   IF ((SIG_in(2)='0') OR ((SIG_in(3)='0') AND (SIG_in(1)='0') AND (SIG_in(0)='0'))) THEN
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--   IF ((SIG_in(2)='0') OR ((SIG_in(3)='0') AND (SIG_in(2)='1') AND (SIG_in(1)='0') AND (SIG_in(0)='0'))) THEN
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   IF (SIG_in(2)='0') THEN
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                SIG_out <= SIG_in;
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   ELSE
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                SIG_out <= (SIG_in(SIG_width-1 DOWNTO 3) + 1) & "000";
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        END IF;
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END PROCESS;
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END FPround;
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