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[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [common/] [packfp_packfp.vhd] - Blame information for rev 5

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Line No. Rev Author Line
1 3 gmarcus
--
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-- VHDL Architecture HAVOC.PackFP.PackFP
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--
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-- Created:
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--          by - Guillermo
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--          at - ITESM, 09:57:50 07/16/03
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2002.1b (Build 7)
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--
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-- hds interface_start
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY PackFP IS
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   PORT(
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      SIGN  : IN     std_logic;
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      EXP   : IN     std_logic_vector (7 DOWNTO 0);
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      SIG   : IN     std_logic_vector (22 DOWNTO 0);
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      isNaN : IN     std_logic;
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      isINF : IN     std_logic;
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          isZ   : IN     std_logic;
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      FP    : OUT    std_logic_vector (31 DOWNTO 0)
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   );
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-- Declarations
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END PackFP ;
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-- hds interface_end
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ARCHITECTURE PackFP OF PackFP IS
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BEGIN
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PROCESS(isNaN,isINF,isZ,SIGN,EXP,SIG)
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BEGIN
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        IF (isNaN='1') THEN
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                FP(31) <= SIGN;
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                FP(30 DOWNTO 23) <= X"FF";
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                FP(22 DOWNTO 0) <= "100" & X"00000";
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        ELSIF (isINF='1') THEN
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                FP(31) <= SIGN;
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                FP(30 DOWNTO 23) <= X"FF";
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                FP(22 DOWNTO 0) <= (OTHERS => '0');
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        ELSIF (isZ='1') THEN
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                FP(31) <= SIGN;
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                FP(30 DOWNTO 23) <= X"00";
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                FP(22 DOWNTO 0) <= (OTHERS => '0');
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    ELSE
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                FP(31) <= SIGN;
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                FP(30 DOWNTO 23) <= EXP;
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                FP(22 DOWNTO 0) <= SIG;
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        END IF;
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END PROCESS;
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END PackFP;
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