OpenCores
URL https://opencores.org/ocsvn/fpuvhdl/fpuvhdl/trunk

Subversion Repositories fpuvhdl

[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [multiplier/] [fpmul_pipeline.vhd] - Blame information for rev 5

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 3 gmarcus 
-- VHDL Entity HAVOC.FPmul.symbol
2 
--
3 
-- Created by
4 
-- Guillermo Marcus, gmarcus@ieee.org
5 
-- using Mentor Graphics FPGA Advantage tools.
6 
--
7 
-- Visit "http://fpga.mty.itesm.mx" for more info.
8 
--
9 
-- 2003-2004. V1.0
10 
--
11 
 
12 
LIBRARY ieee;
13 
USE ieee.std_logic_1164.all;
14 
USE ieee.std_logic_arith.all;
15 
 
16 
ENTITY FPmul IS
17 
   PORT(
18 
      FP_A : IN     std_logic_vector (31 DOWNTO 0);
19 
      FP_B : IN     std_logic_vector (31 DOWNTO 0);
20 
      clk  : IN     std_logic;
21 
      FP_Z : OUT    std_logic_vector (31 DOWNTO 0)
22 
   );
23 
 
24 
-- Declarations
25 
 
26 
END FPmul ;
27 
 
28 
--
29 
-- VHDL Architecture HAVOC.FPmul.pipeline
30 
--
31 
-- Created by
32 
-- Guillermo Marcus, gmarcus@ieee.org
33 
-- using Mentor Graphics FPGA Advantage tools.
34 
--
35 
-- Visit "http://fpga.mty.itesm.mx" for more info.
36 
--
37 
-- Copyright 2003-2004. V1.0
38 
--
39 
 
40 
 
41 
LIBRARY ieee;
42 
USE ieee.std_logic_1164.all;
43 
USE ieee.std_logic_arith.all;
44 
 
45 
ARCHITECTURE pipeline OF FPmul IS
46 
 
47 
   -- Architecture declarations
48 
 
49 
   -- Internal signal declarations
50 
   SIGNAL A_EXP           : std_logic_vector(7 DOWNTO 0);
51 
   SIGNAL A_SIG           : std_logic_vector(31 DOWNTO 0);
52 
   SIGNAL B_EXP           : std_logic_vector(7 DOWNTO 0);
53 
   SIGNAL B_SIG           : std_logic_vector(31 DOWNTO 0);
54 
   SIGNAL EXP_in          : std_logic_vector(7 DOWNTO 0);
55 
   SIGNAL EXP_neg         : std_logic;
56 
   SIGNAL EXP_neg_stage2  : std_logic;
57 
   SIGNAL EXP_out_round   : std_logic_vector(7 DOWNTO 0);
58 
   SIGNAL EXP_pos         : std_logic;
59 
   SIGNAL EXP_pos_stage2  : std_logic;
60 
   SIGNAL SIGN_out        : std_logic;
61 
   SIGNAL SIGN_out_stage1 : std_logic;
62 
   SIGNAL SIGN_out_stage2 : std_logic;
63 
   SIGNAL SIG_in          : std_logic_vector(27 DOWNTO 0);
64 
   SIGNAL SIG_out_round   : std_logic_vector(27 DOWNTO 0);
65 
   SIGNAL isINF_stage1    : std_logic;
66 
   SIGNAL isINF_stage2    : std_logic;
67 
   SIGNAL isINF_tab       : std_logic;
68 
   SIGNAL isNaN           : std_logic;
69 
   SIGNAL isNaN_stage1    : std_logic;
70 
   SIGNAL isNaN_stage2    : std_logic;
71 
   SIGNAL isZ_tab         : std_logic;
72 
   SIGNAL isZ_tab_stage1  : std_logic;
73 
   SIGNAL isZ_tab_stage2  : std_logic;
74 
 
75 
 
76 
   -- Component Declarations
77 
   COMPONENT FPmul_stage1
78 
   PORT (
79 
      FP_A            : IN     std_logic_vector (31 DOWNTO 0);
80 
      FP_B            : IN     std_logic_vector (31 DOWNTO 0);
81 
      clk             : IN     std_logic ;
82 
      A_EXP           : OUT    std_logic_vector (7 DOWNTO 0);
83 
      A_SIG           : OUT    std_logic_vector (31 DOWNTO 0);
84 
      B_EXP           : OUT    std_logic_vector (7 DOWNTO 0);
85 
      B_SIG           : OUT    std_logic_vector (31 DOWNTO 0);
86 
      SIGN_out_stage1 : OUT    std_logic ;
87 
      isINF_stage1    : OUT    std_logic ;
88 
      isNaN_stage1    : OUT    std_logic ;
89 
      isZ_tab_stage1  : OUT    std_logic
90 
   );
91 
   END COMPONENT;
92 
   COMPONENT FPmul_stage2
93 
   PORT (
94 
      A_EXP           : IN     std_logic_vector (7 DOWNTO 0);
95 
      A_SIG           : IN     std_logic_vector (31 DOWNTO 0);
96 
      B_EXP           : IN     std_logic_vector (7 DOWNTO 0);
97 
      B_SIG           : IN     std_logic_vector (31 DOWNTO 0);
98 
      SIGN_out_stage1 : IN     std_logic ;
99 
      clk             : IN     std_logic ;
100 
      isINF_stage1    : IN     std_logic ;
101 
      isNaN_stage1    : IN     std_logic ;
102 
      isZ_tab_stage1  : IN     std_logic ;
103 
      EXP_in          : OUT    std_logic_vector (7 DOWNTO 0);
104 
      EXP_neg_stage2  : OUT    std_logic ;
105 
      EXP_pos_stage2  : OUT    std_logic ;
106 
      SIGN_out_stage2 : OUT    std_logic ;
107 
      SIG_in          : OUT    std_logic_vector (27 DOWNTO 0);
108 
      isINF_stage2    : OUT    std_logic ;
109 
      isNaN_stage2    : OUT    std_logic ;
110 
      isZ_tab_stage2  : OUT    std_logic
111 
   );
112 
   END COMPONENT;
113 
   COMPONENT FPmul_stage3
114 
   PORT (
115 
      EXP_in          : IN     std_logic_vector (7 DOWNTO 0);
116 
      EXP_neg_stage2  : IN     std_logic ;
117 
      EXP_pos_stage2  : IN     std_logic ;
118 
      SIGN_out_stage2 : IN     std_logic ;
119 
      SIG_in          : IN     std_logic_vector (27 DOWNTO 0);
120 
      clk             : IN     std_logic ;
121 
      isINF_stage2    : IN     std_logic ;
122 
      isNaN_stage2    : IN     std_logic ;
123 
      isZ_tab_stage2  : IN     std_logic ;
124 
      EXP_neg         : OUT    std_logic ;
125 
      EXP_out_round   : OUT    std_logic_vector (7 DOWNTO 0);
126 
      EXP_pos         : OUT    std_logic ;
127 
      SIGN_out        : OUT    std_logic ;
128 
      SIG_out_round   : OUT    std_logic_vector (27 DOWNTO 0);
129 
      isINF_tab       : OUT    std_logic ;
130 
      isNaN           : OUT    std_logic ;
131 
      isZ_tab         : OUT    std_logic
132 
   );
133 
   END COMPONENT;
134 
   COMPONENT FPmul_stage4
135 
   PORT (
136 
      EXP_neg       : IN     std_logic ;
137 
      EXP_out_round : IN     std_logic_vector (7 DOWNTO 0);
138 
      EXP_pos       : IN     std_logic ;
139 
      SIGN_out      : IN     std_logic ;
140 
      SIG_out_round : IN     std_logic_vector (27 DOWNTO 0);
141 
      clk           : IN     std_logic ;
142 
      isINF_tab     : IN     std_logic ;
143 
      isNaN         : IN     std_logic ;
144 
      isZ_tab       : IN     std_logic ;
145 
      FP_Z          : OUT    std_logic_vector (31 DOWNTO 0)
146 
   );
147 
   END COMPONENT;
148 
 
149 
   -- Optional embedded configurations
150 
   -- pragma synthesis_off
151 4 gmarcus 
   FOR ALL : FPmul_stage1 USE ENTITY work.FPmul_stage1;
152 
   FOR ALL : FPmul_stage2 USE ENTITY work.FPmul_stage2;
153 
   FOR ALL : FPmul_stage3 USE ENTITY work.FPmul_stage3;
154 
   FOR ALL : FPmul_stage4 USE ENTITY work.FPmul_stage4;
155 3 gmarcus 
   -- pragma synthesis_on
156 
 
157 
 
158 
BEGIN
159 
 
160 
   -- Instance port mappings.
161 
   I1 : FPmul_stage1
162 
      PORT MAP (
163 
         FP_A            => FP_A,
164 
         FP_B            => FP_B,
165 
         clk             => clk,
166 
         A_EXP           => A_EXP,
167 
         A_SIG           => A_SIG,
168 
         B_EXP           => B_EXP,
169 
         B_SIG           => B_SIG,
170 
         SIGN_out_stage1 => SIGN_out_stage1,
171 
         isINF_stage1    => isINF_stage1,
172 
         isNaN_stage1    => isNaN_stage1,
173 
         isZ_tab_stage1  => isZ_tab_stage1
174 
      );
175 
   I2 : FPmul_stage2
176 
      PORT MAP (
177 
         A_EXP           => A_EXP,
178 
         A_SIG           => A_SIG,
179 
         B_EXP           => B_EXP,
180 
         B_SIG           => B_SIG,
181 
         SIGN_out_stage1 => SIGN_out_stage1,
182 
         clk             => clk,
183 
         isINF_stage1    => isINF_stage1,
184 
         isNaN_stage1    => isNaN_stage1,
185 
         isZ_tab_stage1  => isZ_tab_stage1,
186 
         EXP_in          => EXP_in,
187 
         EXP_neg_stage2  => EXP_neg_stage2,
188 
         EXP_pos_stage2  => EXP_pos_stage2,
189 
         SIGN_out_stage2 => SIGN_out_stage2,
190 
         SIG_in          => SIG_in,
191 
         isINF_stage2    => isINF_stage2,
192 
         isNaN_stage2    => isNaN_stage2,
193 
         isZ_tab_stage2  => isZ_tab_stage2
194 
      );
195 
   I3 : FPmul_stage3
196 
      PORT MAP (
197 
         EXP_in          => EXP_in,
198 
         EXP_neg_stage2  => EXP_neg_stage2,
199 
         EXP_pos_stage2  => EXP_pos_stage2,
200 
         SIGN_out_stage2 => SIGN_out_stage2,
201 
         SIG_in          => SIG_in,
202 
         clk             => clk,
203 
         isINF_stage2    => isINF_stage2,
204 
         isNaN_stage2    => isNaN_stage2,
205 
         isZ_tab_stage2  => isZ_tab_stage2,
206 
         EXP_neg         => EXP_neg,
207 
         EXP_out_round   => EXP_out_round,
208 
         EXP_pos         => EXP_pos,
209 
         SIGN_out        => SIGN_out,
210 
         SIG_out_round   => SIG_out_round,
211 
         isINF_tab       => isINF_tab,
212 
         isNaN           => isNaN,
213 
         isZ_tab         => isZ_tab
214 
      );
215 
   I4 : FPmul_stage4
216 
      PORT MAP (
217 
         EXP_neg       => EXP_neg,
218 
         EXP_out_round => EXP_out_round,
219 
         EXP_pos       => EXP_pos,
220 
         SIGN_out      => SIGN_out,
221 
         SIG_out_round => SIG_out_round,
222 
         clk           => clk,
223 
         isINF_tab     => isINF_tab,
224 
         isNaN         => isNaN,
225 
         isZ_tab       => isZ_tab,
226 
         FP_Z          => FP_Z
227 
      );
228 
 
229 
END pipeline;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.