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[/] [fpuvhdl/] [trunk/] [fpuvhdl/] [multiplier/] [fpmul_pipeline.vhd] - Blame information for rev 3

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1 3 gmarcus 
-- VHDL Entity HAVOC.FPmul.symbol
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--
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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-- 2003-2004. V1.0
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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ENTITY FPmul IS
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   PORT(
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      FP_A : IN     std_logic_vector (31 DOWNTO 0);
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      FP_B : IN     std_logic_vector (31 DOWNTO 0);
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      clk  : IN     std_logic;
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      FP_Z : OUT    std_logic_vector (31 DOWNTO 0)
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   );
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-- Declarations
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END FPmul ;
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--
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-- VHDL Architecture HAVOC.FPmul.pipeline
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--
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-- Created by
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-- Guillermo Marcus, gmarcus@ieee.org
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-- using Mentor Graphics FPGA Advantage tools.
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--
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-- Visit "http://fpga.mty.itesm.mx" for more info.
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--
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-- Copyright 2003-2004. V1.0
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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LIBRARY HAVOC;
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ARCHITECTURE pipeline OF FPmul IS
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   -- Architecture declarations
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   -- Internal signal declarations
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   SIGNAL A_EXP           : std_logic_vector(7 DOWNTO 0);
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   SIGNAL A_SIG           : std_logic_vector(31 DOWNTO 0);
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   SIGNAL B_EXP           : std_logic_vector(7 DOWNTO 0);
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   SIGNAL B_SIG           : std_logic_vector(31 DOWNTO 0);
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   SIGNAL EXP_in          : std_logic_vector(7 DOWNTO 0);
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   SIGNAL EXP_neg         : std_logic;
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   SIGNAL EXP_neg_stage2  : std_logic;
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   SIGNAL EXP_out_round   : std_logic_vector(7 DOWNTO 0);
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   SIGNAL EXP_pos         : std_logic;
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   SIGNAL EXP_pos_stage2  : std_logic;
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   SIGNAL SIGN_out        : std_logic;
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   SIGNAL SIGN_out_stage1 : std_logic;
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   SIGNAL SIGN_out_stage2 : std_logic;
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   SIGNAL SIG_in          : std_logic_vector(27 DOWNTO 0);
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   SIGNAL SIG_out_round   : std_logic_vector(27 DOWNTO 0);
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   SIGNAL isINF_stage1    : std_logic;
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   SIGNAL isINF_stage2    : std_logic;
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   SIGNAL isINF_tab       : std_logic;
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   SIGNAL isNaN           : std_logic;
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   SIGNAL isNaN_stage1    : std_logic;
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   SIGNAL isNaN_stage2    : std_logic;
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   SIGNAL isZ_tab         : std_logic;
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   SIGNAL isZ_tab_stage1  : std_logic;
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   SIGNAL isZ_tab_stage2  : std_logic;
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   -- Component Declarations
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   COMPONENT FPmul_stage1
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   PORT (
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      FP_A            : IN     std_logic_vector (31 DOWNTO 0);
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      FP_B            : IN     std_logic_vector (31 DOWNTO 0);
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      clk             : IN     std_logic ;
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      A_EXP           : OUT    std_logic_vector (7 DOWNTO 0);
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      A_SIG           : OUT    std_logic_vector (31 DOWNTO 0);
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      B_EXP           : OUT    std_logic_vector (7 DOWNTO 0);
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      B_SIG           : OUT    std_logic_vector (31 DOWNTO 0);
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      SIGN_out_stage1 : OUT    std_logic ;
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      isINF_stage1    : OUT    std_logic ;
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      isNaN_stage1    : OUT    std_logic ;
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      isZ_tab_stage1  : OUT    std_logic
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   );
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   END COMPONENT;
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   COMPONENT FPmul_stage2
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   PORT (
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      A_EXP           : IN     std_logic_vector (7 DOWNTO 0);
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      A_SIG           : IN     std_logic_vector (31 DOWNTO 0);
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      B_EXP           : IN     std_logic_vector (7 DOWNTO 0);
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      B_SIG           : IN     std_logic_vector (31 DOWNTO 0);
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      SIGN_out_stage1 : IN     std_logic ;
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      clk             : IN     std_logic ;
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      isINF_stage1    : IN     std_logic ;
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      isNaN_stage1    : IN     std_logic ;
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      isZ_tab_stage1  : IN     std_logic ;
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      EXP_in          : OUT    std_logic_vector (7 DOWNTO 0);
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      EXP_neg_stage2  : OUT    std_logic ;
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      EXP_pos_stage2  : OUT    std_logic ;
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      SIGN_out_stage2 : OUT    std_logic ;
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      SIG_in          : OUT    std_logic_vector (27 DOWNTO 0);
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      isINF_stage2    : OUT    std_logic ;
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      isNaN_stage2    : OUT    std_logic ;
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      isZ_tab_stage2  : OUT    std_logic
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   );
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   END COMPONENT;
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   COMPONENT FPmul_stage3
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   PORT (
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      EXP_in          : IN     std_logic_vector (7 DOWNTO 0);
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      EXP_neg_stage2  : IN     std_logic ;
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      EXP_pos_stage2  : IN     std_logic ;
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      SIGN_out_stage2 : IN     std_logic ;
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      SIG_in          : IN     std_logic_vector (27 DOWNTO 0);
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      clk             : IN     std_logic ;
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      isINF_stage2    : IN     std_logic ;
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      isNaN_stage2    : IN     std_logic ;
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      isZ_tab_stage2  : IN     std_logic ;
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      EXP_neg         : OUT    std_logic ;
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      EXP_out_round   : OUT    std_logic_vector (7 DOWNTO 0);
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      EXP_pos         : OUT    std_logic ;
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      SIGN_out        : OUT    std_logic ;
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      SIG_out_round   : OUT    std_logic_vector (27 DOWNTO 0);
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      isINF_tab       : OUT    std_logic ;
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      isNaN           : OUT    std_logic ;
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      isZ_tab         : OUT    std_logic
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   );
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   END COMPONENT;
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   COMPONENT FPmul_stage4
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   PORT (
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      EXP_neg       : IN     std_logic ;
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      EXP_out_round : IN     std_logic_vector (7 DOWNTO 0);
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      EXP_pos       : IN     std_logic ;
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      SIGN_out      : IN     std_logic ;
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      SIG_out_round : IN     std_logic_vector (27 DOWNTO 0);
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      clk           : IN     std_logic ;
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      isINF_tab     : IN     std_logic ;
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      isNaN         : IN     std_logic ;
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      isZ_tab       : IN     std_logic ;
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      FP_Z          : OUT    std_logic_vector (31 DOWNTO 0)
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   );
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   END COMPONENT;
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   -- Optional embedded configurations
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   -- pragma synthesis_off
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   FOR ALL : FPmul_stage1 USE ENTITY HAVOC.FPmul_stage1;
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   FOR ALL : FPmul_stage2 USE ENTITY HAVOC.FPmul_stage2;
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   FOR ALL : FPmul_stage3 USE ENTITY HAVOC.FPmul_stage3;
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   FOR ALL : FPmul_stage4 USE ENTITY HAVOC.FPmul_stage4;
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   -- pragma synthesis_on
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BEGIN
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   -- Instance port mappings.
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   I1 : FPmul_stage1
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      PORT MAP (
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         FP_A            => FP_A,
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         FP_B            => FP_B,
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         clk             => clk,
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         A_EXP           => A_EXP,
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         A_SIG           => A_SIG,
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         B_EXP           => B_EXP,
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         B_SIG           => B_SIG,
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         SIGN_out_stage1 => SIGN_out_stage1,
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         isINF_stage1    => isINF_stage1,
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         isNaN_stage1    => isNaN_stage1,
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         isZ_tab_stage1  => isZ_tab_stage1
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      );
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   I2 : FPmul_stage2
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      PORT MAP (
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         A_EXP           => A_EXP,
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         A_SIG           => A_SIG,
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         B_EXP           => B_EXP,
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         B_SIG           => B_SIG,
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         SIGN_out_stage1 => SIGN_out_stage1,
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         clk             => clk,
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         isINF_stage1    => isINF_stage1,
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         isNaN_stage1    => isNaN_stage1,
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         isZ_tab_stage1  => isZ_tab_stage1,
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         EXP_in          => EXP_in,
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         EXP_neg_stage2  => EXP_neg_stage2,
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         EXP_pos_stage2  => EXP_pos_stage2,
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         SIGN_out_stage2 => SIGN_out_stage2,
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         SIG_in          => SIG_in,
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         isINF_stage2    => isINF_stage2,
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         isNaN_stage2    => isNaN_stage2,
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         isZ_tab_stage2  => isZ_tab_stage2
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      );
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   I3 : FPmul_stage3
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      PORT MAP (
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         EXP_in          => EXP_in,
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         EXP_neg_stage2  => EXP_neg_stage2,
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         EXP_pos_stage2  => EXP_pos_stage2,
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         SIGN_out_stage2 => SIGN_out_stage2,
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         SIG_in          => SIG_in,
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         clk             => clk,
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         isINF_stage2    => isINF_stage2,
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         isNaN_stage2    => isNaN_stage2,
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         isZ_tab_stage2  => isZ_tab_stage2,
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         EXP_neg         => EXP_neg,
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         EXP_out_round   => EXP_out_round,
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         EXP_pos         => EXP_pos,
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         SIGN_out        => SIGN_out,
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         SIG_out_round   => SIG_out_round,
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         isINF_tab       => isINF_tab,
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         isNaN           => isNaN,
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         isZ_tab         => isZ_tab
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      );
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   I4 : FPmul_stage4
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      PORT MAP (
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         EXP_neg       => EXP_neg,
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         EXP_out_round => EXP_out_round,
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         EXP_pos       => EXP_pos,
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         SIGN_out      => SIGN_out,
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         SIG_out_round => SIG_out_round,
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         clk           => clk,
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         isINF_tab     => isINF_tab,
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         isNaN         => isNaN,
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         isZ_tab       => isZ_tab,
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         FP_Z          => FP_Z
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      );
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END pipeline;

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