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[/] [freq_div/] [trunk/] [rtl/] [odd.v] - Blame information for rev 2

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`include "defines.v"
 
module odd(clk, out, P, reset);
 
        input clk;      // slow clock
        output out;
        input [`SIZE-1:0] P;
        input reset;
 
        reg [`SIZE-1:0] counter;
        reg [`SIZE-1:0] counter2;
        reg out_counter;
        reg out_counter2;
        reg rst_pulse;
        reg [`SIZE-1:0] old_P;
        wire not_zero;
 
        assign out = out_counter2 ^ out_counter;
 
        always @(posedge clk)
        begin
                if(reset | rst_pulse)
                begin
                        counter <= P;
                        out_counter <= 1;
                end
                else
                begin
                        if(counter == 1)
                        begin
                                counter <= P;
                                out_counter <= ~out_counter;
                        end
                        else
                        begin
                                counter <= counter-1;
                        end
                end
        end
 
        reg [`SIZE-1:0] initial_begin;
        wire [`SIZE:0] interm_3;
        assign interm_3 = {1'b0,P} + 3;
 
        always @(negedge clk)
        begin
                if(reset | rst_pulse)
                begin
                        counter2 <= P;
                        initial_begin <= interm_3[`SIZE:1];
                        out_counter2 <= 1;
                end
                else if(initial_begin <= 1)
                begin
                        if(counter2 == 1)
                        begin
                                counter2 <= P;
                                out_counter2 <= ~out_counter2;
                        end
                        else
                        begin
                                counter2 <= counter2-1;
                        end
                end
                else
                begin
                        initial_begin <= initial_begin - 1;
                end
        end
 
        always @(posedge clk or posedge reset)
        begin
                if(reset)
                begin
                        rst_pulse <= 0;
                end
                else
                begin
                        if(P != old_P)
                        begin
                                rst_pulse <= 1;
                        end
                        else
                        begin
                                rst_pulse <= 0;
                        end
                        old_P <= P;
                end
        end
 
 
endmodule //odd

Line No.	Rev	Author	Line
1	2	joecrop
2			`include "defines.v"
3
4			`module odd(clk, out, P, reset);`
5
6			`input clk; // slow clock`
7			`output out;`
8			input [`SIZE-1:0] P;
9			`input reset;`
10
11			reg [`SIZE-1:0] counter;
12			reg [`SIZE-1:0] counter2;
13			`reg out_counter;`
14			`reg out_counter2;`
15			`reg rst_pulse;`
16			reg [`SIZE-1:0] old_P;
17			`wire not_zero;`
18
19			`assign out = out_counter2 ^ out_counter;`
20
21			`always @(posedge clk)`
22			`begin`
23			`if(reset \| rst_pulse)`
24			`begin`
25			`counter <= P;`
26			`out_counter <= 1;`
27			`end`
28			`else`
29			`begin`
30			`if(counter == 1)`
31			`begin`
32			`counter <= P;`
33			`out_counter <= ~out_counter;`
34			`end`
35			`else`
36			`begin`
37			`counter <= counter-1;`
38			`end`
39			`end`
40			`end`
41
42			reg [`SIZE-1:0] initial_begin;
43			wire [`SIZE:0] interm_3;
44			`assign interm_3 = {1'b0,P} + 3;`
45
46			`always @(negedge clk)`
47			`begin`
48			`if(reset \| rst_pulse)`
49			`begin`
50			`counter2 <= P;`
51			initial_begin <= interm_3[`SIZE:1];
52			`out_counter2 <= 1;`
53			`end`
54			`else if(initial_begin <= 1)`
55			`begin`
56			`if(counter2 == 1)`
57			`begin`
58			`counter2 <= P;`
59			`out_counter2 <= ~out_counter2;`
60			`end`
61			`else`
62			`begin`
63			`counter2 <= counter2-1;`
64			`end`
65			`end`
66			`else`
67			`begin`
68			`initial_begin <= initial_begin - 1;`
69			`end`
70			`end`
71
72			`always @(posedge clk or posedge reset)`
73			`begin`
74			`if(reset)`
75			`begin`
76			`rst_pulse <= 0;`
77			`end`
78			`else`
79			`begin`
80			`if(P != old_P)`
81			`begin`
82			`rst_pulse <= 1;`
83			`end`
84			`else`
85			`begin`
86			`rst_pulse <= 0;`
87			`end`
88			`old_P <= P;`
89			`end`
90			`end`
91
92
93			`endmodule //odd`

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[/] [freq_div/] [trunk/] [rtl/] [odd.v] - Blame information for rev 2