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[/] [freq_div/] [trunk/] [rtl/] [odd.v] - Blame information for rev 3

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`include "defines.v"
 
module odd(clk, out, P, reset, enable);
 
        input clk;      // slow clock
        output out;
        input [`SIZE-1:0] P;
        input reset;
        input enable;
 
        reg [`SIZE-1:0] counter;
        reg [`SIZE-1:0] counter2;
        reg out_counter;
        reg out_counter2;
        reg rst_pulse;
        reg [`SIZE-1:0] old_P;
        wire not_zero;
 
        assign out = out_counter2 ^ out_counter;
 
        always @(posedge clk)
        begin
                if(reset | rst_pulse)
                begin
                        counter <= P;
                        out_counter <= 1;
                end
                else if (enable)
                begin
                        if(counter == 1)
                        begin
                                counter <= P;
                                out_counter <= ~out_counter;
                        end
                        else
                        begin
                                counter <= counter-1;
                        end
                end
        end
 
        reg [`SIZE-1:0] initial_begin;
        wire [`SIZE:0] interm_3;
        assign interm_3 = {1'b0,P} + 3;
 
        always @(negedge clk)
        begin
                if(reset | rst_pulse)
                begin
                        counter2 <= P;
                        initial_begin <= interm_3[`SIZE:1];
                        out_counter2 <= 1;
                end
                else if(initial_begin <= 1 && enable)
                begin
                        if(counter2 == 1)
                        begin
                                counter2 <= P;
                                out_counter2 <= ~out_counter2;
                        end
                        else
                        begin
                                counter2 <= counter2-1;
                        end
                end
                else if(enable)
                begin
                        initial_begin <= initial_begin - 1;
                end
        end
 
        always @(posedge clk or posedge reset)
        begin
                if(reset)
                begin
                        rst_pulse <= 0;
                end
                else if(enable)
                begin
                        if(P != old_P)
                        begin
                                rst_pulse <= 1;
                        end
                        else
                        begin
                                rst_pulse <= 0;
                        end
                        old_P <= P;
                end
        end
 
endmodule //odd

Line No.	Rev	Author	Line
1	2	joecrop
2			`include "defines.v"
3
4	3	joecrop	`module odd(clk, out, P, reset, enable);`
5	2	joecrop
6			`input clk; // slow clock`
7			`output out;`
8			input [`SIZE-1:0] P;
9			`input reset;`
10	3	joecrop	`input enable;`
11	2	joecrop
12			reg [`SIZE-1:0] counter;
13			reg [`SIZE-1:0] counter2;
14			`reg out_counter;`
15			`reg out_counter2;`
16			`reg rst_pulse;`
17			reg [`SIZE-1:0] old_P;
18			`wire not_zero;`
19
20			`assign out = out_counter2 ^ out_counter;`
21
22			`always @(posedge clk)`
23			`begin`
24			`if(reset \| rst_pulse)`
25			`begin`
26			`counter <= P;`
27			`out_counter <= 1;`
28			`end`
29	3	joecrop	`else if (enable)`
30	2	joecrop	`begin`
31			`if(counter == 1)`
32			`begin`
33			`counter <= P;`
34			`out_counter <= ~out_counter;`
35			`end`
36			`else`
37			`begin`
38			`counter <= counter-1;`
39			`end`
40			`end`
41			`end`
42
43			reg [`SIZE-1:0] initial_begin;
44			wire [`SIZE:0] interm_3;
45			`assign interm_3 = {1'b0,P} + 3;`
46
47			`always @(negedge clk)`
48			`begin`
49			`if(reset \| rst_pulse)`
50			`begin`
51			`counter2 <= P;`
52			initial_begin <= interm_3[`SIZE:1];
53			`out_counter2 <= 1;`
54			`end`
55	3	joecrop	`else if(initial_begin <= 1 && enable)`
56	2	joecrop	`begin`
57			`if(counter2 == 1)`
58			`begin`
59			`counter2 <= P;`
60			`out_counter2 <= ~out_counter2;`
61			`end`
62			`else`
63			`begin`
64			`counter2 <= counter2-1;`
65			`end`
66			`end`
67	3	joecrop	`else if(enable)`
68	2	joecrop	`begin`
69			`initial_begin <= initial_begin - 1;`
70			`end`
71			`end`
72
73			`always @(posedge clk or posedge reset)`
74			`begin`
75			`if(reset)`
76			`begin`
77			`rst_pulse <= 0;`
78			`end`
79	3	joecrop	`else if(enable)`
80	2	joecrop	`begin`
81			`if(P != old_P)`
82			`begin`
83			`rst_pulse <= 1;`
84			`end`
85			`else`
86			`begin`
87			`rst_pulse <= 0;`
88			`end`
89			`old_P <= P;`
90			`end`
91			`end`
92
93			`endmodule //odd`

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[/] [freq_div/] [trunk/] [rtl/] [odd.v] - Blame information for rev 3