This component allows an FTDI FT601 USB3.0 device to act as a high-performance AXI4 bus master.
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![Block Diagram](docs/block_diagram.png)
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##### Features
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* Interfaces to FTDI FT601 USB FIFO device.
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* AXI-4 bus master with support for incrementing bursts and multiple outstanding transactions (for high performance).
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* 2 x 8KB FIFO (which map to BlockRAMs in Xilinx FPGAs).
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* Designed to work @ 100MHz in FPGA (as per FTDI FT60x max clock rate).
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* Uses FT60x 245 mode protocol (32-bit mode).
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* Support for 32 GPIO.
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* Capable of sustained pipelined AXI-4 burst **reads @ 170MB/s** and **writes @ 230MB/s**.
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##### Performance
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![Block Diagram](docs/performance.png)
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##### Testing
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Verified under simulation (constrained random testing), and tested on a Xilinx Artix 7 with blockRAM and DDR3 targets on the LambdaConcept USB2Sniffer Board (connected to a Linux host PC).