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[/] [ft816float/] [trunk/] [posit_test_bench/] [positDiv_tb.v] - Blame information for rev 59

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Line No. Rev Author Line
1 43 robfinch
`timescale 1ns / 1ps
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module positDiv_tb_v;
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function [31:0] log2;
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input reg [31:0] value;
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        begin
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        value = value-1;
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        for (log2=0; value>0; log2=log2+1)
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                value = value>>1;
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        end
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endfunction
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parameter N=64;
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parameter E=8;
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parameter Bs=log2(N);
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parameter es = 3;
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reg [N-1:0] in;
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reg clk;
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reg [31:0] cnt = 0;
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wire [N-1:0] out, out2, out3;
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reg [N-1:0] a1, b1;
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wire [N-1:0] a, b;
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wire [N-1:0] p, fsum, fa, fb, ad, bd, psumd, out2d, p1;
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wire i,z,d,i1,z1,d1;
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wire done;
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reg start;
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// Instantiate the Unit Under Test (UUT)
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intToPosit #(.PSTWID(N), .es(es)) u1a (.i(a1), .o(a));
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intToPosit #(.PSTWID(N), .es(es)) u1b (.i(b1), .o(b));
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positDivide #(.PSTWID(N), .es(es)) udiv1 (clk, 1'b1, a, b, p, start, d, z, i);
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posit_div #(.N(N),.es(es)) udiv2 (a, b, start, p1, i1, z1, d1);
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delay2 #(N) ud1 (.clk(clk), .ce(1'b1), .i(a), .o(ad));
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delay2 #(N) ud2 (.clk(clk), .ce(1'b1), .i(a), .o(bd));
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delay2 #(N) ud3 (.clk(clk), .ce(1'b1), .i(psum), .o(psumd));
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delay2 #(N) ud4 (.clk(clk), .ce(1'b1), .i(out2), .o(out2d));
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        initial begin
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          a1 = $urandom(1);
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          b1 = $urandom(2);
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          cnt = 0;
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                // Initialize Inputs
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                clk = 1;
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                // Wait 100 ns for global reset to finish
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                #101 in = 32'h0080ffff;
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                #325150
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                $fclose(outfile);
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                $finish;
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        end
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always #5 clk=~clk;
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always @(posedge clk) begin
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start <= 0;
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  cnt = cnt + 1;
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  case(cnt)
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  0:
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    begin
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    start <= 1;
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      a1 = 0;
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      b1 = 0;
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    end
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  1:
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    begin
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      a1 = 0;
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      b1 = 10;
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    end
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  2:
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    begin
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      a1 = 10;
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      b1 = 10;
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    end
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  10: start <= 1;
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  default:
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    begin
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      if (d) begin
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       start <= 1;
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        cnt <= cnt + 1;
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        a1 = $urandom();
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        b1 = $urandom();
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      end
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      else
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        cnt <= cnt;
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    end
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  endcase
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end
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integer outfile;
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initial outfile = $fopen("d:/cores2020/rtf64/v2/rtl/verilog/cpu/pau/test_bench/positDiv_tvo64.txt", "wb");
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  always @(negedge clk) begin
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    if (p!=p1 && d)
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     $fwrite(outfile, "*%h\t%h\t%h\t%h\n",a,b,p,p1);
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    else if (d)
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     $fwrite(outfile, " %h\t%h\t%h\t%h\n",a,b,p,p1);
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  end
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endmodule
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