OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [posit_test_bench/] [positFDP_tb.v] - Blame information for rev 57

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 42 robfinch
`timescale 1ns / 1ps
2
module positFDP_tb_v;
3
 
4
function [31:0] log2;
5
input reg [31:0] value;
6
        begin
7
        value = value-1;
8
        for (log2=0; value>0; log2=log2+1)
9
                value = value>>1;
10
        end
11
endfunction
12
 
13
parameter N=32;
14
parameter E=8;
15
parameter Bs=log2(N);
16
parameter es = 4;
17
 
18
reg [N-1:0] in;
19
reg clk;
20
reg [5:0] cnt;
21
 
22
wire [N-1:0] out, out2, out3;
23
 
24
reg [N-1:0] a1, b1, c1, d1;
25
wire [N-1:0] a, b, c, d;
26
wire [N-1:0] fdp, p1, p2, s1;
27
wire [N-1:0] p, fsum, fa, fb, ad, bd, psumd, out2d, p1;
28
wire i,z,i1,z1,dn1,dn2,z2,i2,z3,i3;
29
 
30
// Instantiate the Unit Under Test (UUT)
31
 
32
intToPosit #(.PSTWID(N), .es(es)) u1a (.i(a1), .o(a));
33
intToPosit #(.PSTWID(N), .es(es)) u1b (.i(b1), .o(b));
34
intToPosit #(.PSTWID(N), .es(es)) u1c (.i(c1), .o(c));
35
intToPosit #(.PSTWID(N), .es(es)) u1d (.i(d1), .o(d));
36
 
37
positFDP #(.PSTWID(N), .es(es)) ufdp1 (1'b0, a,b,c,d,fdp,z,i);
38
posit_mult #(.N(N),.es(es)) umul3 (a, b, 1'b1, p1, i1, z1, dn1);
39
posit_mult #(.N(N),.es(es)) umul4 (c, d, 1'b1, p2, i2, z2, dn2);
40
positAddsub #(.PSTWID(N),.es(es)) uas1 (1'b0, p1, p2, s1);
41
 
42
delay2 #(N) ud1 (.i(a), .o(ad));
43
delay2 #(N) ud2 (.i(a), .o(bd));
44
delay2 #(N) ud3 (.i(psum), .o(psumd));
45
delay2 #(N) ud4 (.i(out2), .o(out2d));
46
 
47
        initial begin
48
          a1 = $urandom(1);
49
          b1 = $urandom(2);
50
          c1 = $urandom(3);
51
          d1 = $urandom(4);
52
          cnt = 0;
53
                // Initialize Inputs
54
                clk = 1;
55
                // Wait 100 ns for global reset to finish
56
                #101 in = 32'h0080ffff;
57
                #325150
58
                $fclose(outfile);
59
                $finish;
60
        end
61
 
62
always #5 clk=~clk;
63
always @(posedge clk) begin
64
  cnt = cnt + 1;
65
  case(cnt)
66
  0:
67
    begin
68
      a1 = 0;
69
      b1 = 0;
70
      c1 = 0;
71
      d1 = 0;
72
    end
73
  1:
74
    begin
75
      a1 = 0;
76
      b1 = 10;
77
      c1 = 10;
78
      d1 = 0;
79
    end
80
  2:
81
    begin
82
      a1 = 10;
83
      b1 = 10;
84
      c1 = 10;
85
      d1 = 10;
86
    end
87
 
88
  default:
89
    begin
90
      a1 = $urandom();
91
      b1 = $urandom();
92
      c1 = $urandom();
93
      d1 = $urandom();
94
    end
95
  endcase
96
end
97
 
98
integer outfile;
99
initial outfile = $fopen("d:/cores6/Thor2020/v3/rtl/fpu/test_bench/positFDP_tvo32.txt", "wb");
100
  always @(negedge clk) begin
101
    if (s1!=fdp)
102
     $fwrite(outfile, "*%h\t%h\t%h\t%h\t%h\t%h\n",a,b,c,d,s1,fdp);
103
    else
104
     $fwrite(outfile, " %h\t%h\t%h\t%h\t%h\t%h\n",a,b,c,d,s1,fdp);
105
  end
106
 
107
endmodule
108
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.