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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [posit.sv] - Blame information for rev 48

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1 48 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      posit.sv
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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// ============================================================================
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//
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package posit;
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`define PSTWID 32
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parameter PSTWID = `PSTWID;
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localparam es =
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  PSTWID >= 80 ? 4 :
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  PSTWID >= 64 ? 3 :
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  PSTWID >= 52 ? 3 :
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  PSTWID >= 40 ? 3 :
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  PSTWID >= 32 ? 2 :
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  PSTWID >= 24 ? 2 :
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  PSTWID >= 16 ? 1 :
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  PSTWID >= 8 ? 1 :
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localparam rs = $clog2(PSTWID-1);
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endpackage

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