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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positAddsub.sv] - Blame information for rev 44

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      positAddsub.v
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//    - posit number adder/subtracter
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//    - parameterized width
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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// ============================================================================
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`include "positConfig.sv"
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module positAddsub(op, a, b, o);
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`include "positSize.sv"
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localparam rs = $clog2(PSTWID-1);
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input op;
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] b;
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output reg [PSTWID-1:0] o;
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wire sa, sb;
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reg so;
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wire rop;
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wire [rs:0] rgma, rgmb, rgm1, rgm2, argm1, argm2;
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wire rgsa, rgsb, rgs1, rgs2;
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wire [rs+es+1:0] diff;
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wire [es-1:0] expa, expb, exp1, exp2;
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wire [PSTWID-es-1:0] siga, sigb, sig1, sig2;
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wire zera, zerb;
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wire infa, infb;
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wire [PSTWID-1:0] aa, bb;
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wire inf = infa|infb;
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wire zero = zera & zerb;
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positDecompose #(PSTWID,es) u1 (
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  .i(a),
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  .sgn(sa),
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  .rgs(rgsa),
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  .rgm(rgma),
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  .exp(expa),
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  .sig(siga),
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  .zer(zera),
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  .inf(infa)
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);
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positDecompose #(PSTWID,es) u2 (
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  .i(b),
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  .sgn(sb),
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  .rgs(rgsb),
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  .rgm(rgmb),
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  .exp(expb),
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  .sig(sigb),
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  .zer(zerb),
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  .inf(infb)
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);
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assign aa = sa ? -a : a;
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assign bb = sb ? -b : b;
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wire aa_gt_bb = aa >= bb;
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// Determine op really wanted
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assign rop = sa ^ sb ^ op;
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// Sort operand components
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assign rgs1 = aa_gt_bb ? rgsa : rgsb;
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assign rgs2 = aa_gt_bb ? rgsb : rgsa;
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assign rgm1 = aa_gt_bb ? rgma : rgmb;
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assign rgm2 = aa_gt_bb ? rgmb : rgma;
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assign exp1 = aa_gt_bb ? expa : expb;
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assign exp2 = aa_gt_bb ? expb : expa;
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assign sig1 = aa_gt_bb ? siga : sigb;
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assign sig2 = aa_gt_bb ? sigb : siga;
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assign argm1 = rgs1 ? rgm1 : -rgm1;
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assign argm2 = rgs2 ? rgm2 : -rgm2;
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assign diff = {argm1,exp1} - {argm2,exp2};
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wire [rs-1:0] exp_diff = (|diff[es+rs:rs]) ? {rs{1'b1}} : diff[rs-1:0];
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wire [PSTWID*2-1:0] sig2s = {sig2,{PSTWID{1'b0}}} >> exp_diff;
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wire [PSTWID*2-1:0] sig1s = {sig1,{PSTWID{1'b0}}};
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wire [PSTWID*2:0] sig_sd = rop ? sig1s - sig2s : sig1s + sig2s;
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wire [1:0] sigov = sig_sd[PSTWID*2:PSTWID*2-1];
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wire [$clog2(PSTWID-1):0] lzcnt;
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wire [PSTWID-1:0] sigi = {|sigov,sig_sd[PSTWID*2-2:PSTWID]};
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generate begin : gClz
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  case(PSTWID)
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  16: cntlz16 u1 (.i({sigi}), .o(lzcnt));
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  20: cntlz24 u1 (.i({sigi,4'hF}), .o(lzcnt));
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  32: cntlz32 u1 (.i({sigi}), .o(lzcnt));
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  40: cntlz48 u1 (.i({sigi,8'hFF}), .o(lzcnt));
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  52: cntlz64 u1 (.i({sigi,12'hFFF}), .o(lzcnt));
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  64: cntlz64 u1 (.i({sigi}), .o(lzcnt));
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  80: cntlz80 u1 (.i({sigi}), .o(lzcnt));
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  default:  ;
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  endcase
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end
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endgenerate
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//positCntlz #(.PSTWID(PSTWID)) u3 (.i({|sigov,sig_sd[PSTWID-2:0]}), .o(lzcnt));
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wire [PSTWID*2-1:0] sig_ls = sig_sd[PSTWID*2-1:0] << lzcnt;
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wire [rs+1:0] absrgm1 = rgs1 ? rgm1 : -rgm1;  // rgs1 = 1 = positive
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wire [es+rs+1:0] rxtmp;
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wire [es+rs+1:0] rxtmp1;
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wire srxtmp1;
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wire [es+rs:0] abs_rxtmp;
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wire [(es==0 ? 0 : es-1):0] expo;
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wire [rs:0] rgmo;
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generate begin : gEsz
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if (es > 0) begin
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assign rxtmp = {absrgm1,exp1} + es - {{es+1{1'b0}},lzcnt};
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assign rxtmp1 = rxtmp + sigov[1]; // add in overflow if any
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assign srxtmp1 = rxtmp1[es+rs+1];
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assign abs_rxtmp = srxtmp1 ? -rxtmp1 : rxtmp1;
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assign expo = (srxtmp1 & |abs_rxtmp[es-1:0]) ? rxtmp1[es-1:0] : abs_rxtmp[es-1:0];
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assign rgmo = (~srxtmp1 || (|abs_rxtmp[es-1:0])) ? abs_rxtmp[es+rs:es] + 1'b1 : abs_rxtmp[es+rs:es];
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end
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else begin
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assign rxtmp = absrgm1 - {{1{1'b0}},lzcnt};
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assign rxtmp1 = rxtmp + sigov[1]; // add in overflow if any
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assign srxtmp1 = rxtmp1[rs+1];
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assign abs_rxtmp = srxtmp1 ? -rxtmp1 : rxtmp1;
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assign expo = 1'b0;
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assign rgmo = (~srxtmp1) ? abs_rxtmp[rs:0] + 1'b1 : abs_rxtmp[rs:0];
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end
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end
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endgenerate
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// Exponent and Significand Packing
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reg [2*PSTWID-1+3:0] tmp;
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always @*
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case(es)
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0:  tmp = { {PSTWID{~srxtmp1}}, srxtmp1, sig_ls[PSTWID*2-2:PSTWID-2], |sig_ls[PSTWID-3:0]};
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1:  tmp = { {PSTWID{~srxtmp1}}, srxtmp1, expo, sig_ls[PSTWID*2-2:PSTWID-1], |sig_ls[PSTWID-2:0]};
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2:  tmp = { {PSTWID{~srxtmp1}}, srxtmp1, expo, sig_ls[PSTWID*2-2:PSTWID], |sig_ls[PSTWID-1:0]};
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default:  tmp = { {PSTWID{~srxtmp1}}, srxtmp1, expo, sig_ls[PSTWID*2-2:PSTWID+es-2], |sig_ls[PSTWID-1+es-2:0]};
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endcase
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wire [3*PSTWID-1+3:0] tmp1 = {tmp,{PSTWID{1'b0}}} >> rgmo;
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// Rounding
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// Guard, Round, and Sticky
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wire L = tmp1[PSTWID+4], G = tmp1[PSTWID+3], R = tmp1[PSTWID+2], St = |tmp1[PSTWID+1:0],
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     ulp = ((G & (R | St)) | (L & G & ~(R | St)));
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wire [PSTWID-1:0] rnd_ulp = {{PSTWID-1{1'b0}},ulp};
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wire [PSTWID:0] tmp1_rnd_ulp = tmp1[2*PSTWID-1+3:PSTWID+3] + rnd_ulp;
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wire [PSTWID-1:0] tmp1_rnd = (rgmo < PSTWID-es-2) ? tmp1_rnd_ulp[PSTWID-1:0] : tmp1[2*PSTWID-1+3:PSTWID+3];
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// Compute output sign
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always @*
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        casez ({zero,sa,op,sb})
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        4'b0000: so = 1'b0;                     // + + + = +
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        4'b0001: so = !aa_gt_bb;        // + + - = sign of larger
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        4'b0010: so = !aa_gt_bb;        // + - + = sign of larger
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        4'b0011: so = 1'b0;                     // + - - = +
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        4'b0100: so = aa_gt_bb; // - + + = sign of larger
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        4'b0101: so = 1'b1;                     // - + - = -
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        4'b0110: so = 1'b1;                     // - - + = -
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        4'b0111: so = aa_gt_bb; // - - - = sign of larger
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        4'b1???: so = 1'b0;
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        endcase
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wire [PSTWID-1:0] abs_tmp = so ? -tmp1_rnd : tmp1_rnd;
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always @*
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  casez({zero,inf,sig_ls[PSTWID]&1'b0})
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  3'b1??: o = {PSTWID{1'b0}};
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  3'b01?: o = {1'b1,{PSTWID-1{1'b0}}};
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  3'b001: o = {PSTWID{1'b0}};
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  default:  o = {so, abs_tmp[PSTWID-1:1]};
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  endcase
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endmodule

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