OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positDivide.sv] - Blame information for rev 43

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 43 robfinch
// ============================================================================
2
//        __
3
//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
4
//    \  __ /    All rights reserved.
5
//     \/_//     robfinch@finitron.ca
6
//       ||
7
//
8
//      positDivide.sv
9
//    - posit number division function
10
//    - parameterized width
11
//
12
// Parts of this code extracted from the PACoGen project:
13
//    Copyright (c) 2019, Manish Kumar Jaiswal
14
//    All rights reserved.
15
//
16
// BSD 3-Clause License
17
// Redistribution and use in source and binary forms, with or without
18
// modification, are permitted provided that the following conditions are met:
19
//
20
// 1. Redistributions of source code must retain the above copyright notice, this
21
//    list of conditions and the following disclaimer.
22
//
23
// 2. Redistributions in binary form must reproduce the above copyright notice,
24
//    this list of conditions and the following disclaimer in the documentation
25
//    and/or other materials provided with the distribution.
26
//
27
// 3. Neither the name of the copyright holder nor the names of its
28
//    contributors may be used to endorse or promote products derived from
29
//    this software without specific prior written permission.
30
//
31
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
32
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
34
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
35
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
37
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
38
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
40
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41
//
42
// ============================================================================
43
 
44
`include "positConfig.sv"
45
 
46
module positDivide(clk, ce, a, b, o, start, done, zero, inf);
47
`include "positSize.sv"
48
localparam rs = $clog2(PSTWID-1)-1;
49
input clk;
50
input ce;
51
input [PSTWID-1:0] a;
52
input [PSTWID-1:0] b;
53
output reg [PSTWID-1:0] o;
54
input start;
55
output done;
56
output zero;
57
output inf;
58
 
59
localparam N = PSTWID;
60
localparam M = N-es;
61
localparam Bs = $clog2(N-1);
62
localparam NR_Iter = M > 88 ? 4 : M > 44 ? 3 : M > 22 ? 2 : M > 11 ? 1 : 0;             // 2 for 32 bits, 1 for 16 bits, 0 for 8bits
63
localparam NRB = 2**NR_Iter;
64
localparam IW_MAX = 10;                                                 //Max intial approximation storage bit-width
65
localparam IW = 10;//(NRB == 1 ) ? M : (M/NRB*2 + ((M%NRB > 0) ? 1 : 0));       //(must be <= IW_MAX) 1/4th width of Mantissa: inverse width to be used in NR iterations multiplication
66
localparam AW_MAX = 11;                                                 //Max Address width of the intial approximation storage
67
localparam AW = 11;//(NRB == 1) ? M : (M/NRB*2 + ((M%NRB > 0) ? 1 : 0));        //Actual address width used for initial approximation (AW must be <= AW_MAX)
68
 
69
wire sa, sb, so;
70
wire [rs:0] rgma, rgmb;
71
wire rgsa, rgsb;
72
wire [es-1:0] expa, expb;
73
wire [M-1:0] siga, sigb;
74
wire zera, zerb;
75
wire infa, infb;
76
wire inf = infa|zerb;
77
wire zero = zera|infb;
78
 
79
positDecompose #(PSTWID,es) u1 (
80
  .i(a),
81
  .sgn(sa),
82
  .rgs(rgsa),
83
  .rgm(rgma),
84
  .exp(expa),
85
  .sig(siga),
86
  .zer(zera),
87
  .inf(infa)
88
);
89
 
90
positDecompose #(PSTWID,es) u2 (
91
  .i(b),
92
  .sgn(sb),
93
  .rgs(rgsb),
94
  .rgm(rgmb),
95
  .exp(expb),
96
  .sig(sigb),
97
  .zer(zerb),
98
  .inf(infb)
99
);
100
 
101
wire [M:0] m1 = siga << 1;
102
wire [M:0] m2 = sigb << 1;
103
wire [15:0] m2_inv0_tmp;
104
 
105
assign so = sa ^ sb;
106
wire [Bs+1:0] argma = rgsa ? {2'b0,rgma} : -rgma;
107
wire [Bs+1:0] argmb = rgsb ? {2'b0,rgmb} : -rgmb;
108
 
109
generate begin : gDivLut
110
if (M < AW_MAX)
111
div_lut lut1 (.clk(clk), .i({m2[M-1:0],{AW_MAX-M{1'b0}}}), .o(m2_inv0_tmp));
112
else if (M==AW_MAX)
113
div_lut lut1 (.clk(clk), .i(m2[M-1:0]), .o(m2_inv0_tmp));
114
else if (M > AW_MAX)
115
div_lut lut1 (.clk(clk), .i(m2[M-1:M-AW_MAX]), .o(m2_inv0_tmp));
116
end
117
endgenerate
118
 
119
wire [IW:0] m2_inv0;
120
assign m2_inv0 = m2_inv0_tmp[15:5];
121
 
122
wire [2*M+1:0] div_m;
123
wire [2*M+1:0] div_m4;
124
 
125
genvar i;
126
generate begin
127
        wire [2*M+1:0] m2_inv [NR_Iter:0];
128
 
129
        if (NR_Iter > 0) begin
130
                assign m2_inv[0] = {1'b0,m2_inv0,{M-IW{1'b0}},{M{1'b0}}};
131
                wire [2*M+1:0] m2_inv_X_m2 [NR_Iter-1:0];
132
                wire [M+1:0] two_m2_inv_X_m2 [NR_Iter-1:0];
133
                for (i = 0; i < NR_Iter; i=i+1)begin : NR_Iteration
134
                        assign m2_inv_X_m2[i] = {m2_inv[i][2*M:2*M-IW*(i+1)],{2*M-IW*(i+1)-M{1'b0}}} * m2;
135
                        sub_N #(.N(M+1)) uut_sub_m2 ({1'b1,{M{1'b0}}}, {1'b0,m2_inv_X_m2[i][2*M+1:M+3],|m2_inv_X_m2[i][M+2:0]}, two_m2_inv_X_m2[i]);
136
                        assign m2_inv[i+1] = {m2_inv[i][2*M:2*M-IW*(i+1)],{M-IW*(i+1){1'b0}}} * {two_m2_inv_X_m2[i][M-1:0],1'b0};
137
                end
138
        end
139
        else begin
140
                assign m2_inv[0] = {1'b0,m2_inv0,{M{1'b0}}};
141
        end
142
        assign div_m = ~|sigb[M-2:0] ? {1'b0,m1,{M{1'b0}}} : m1 * m2_inv[NR_Iter][2*M:M];
143
end
144
endgenerate
145
 
146
// Put in some pipeline registers to allow tools to retime the NR iterations.
147
delay4 #(M*2+2) ud1 (.clk(clk), .ce(ce), .i(div_m), .o(div_m4));
148
wire d1;
149
delay4 #(1) ud2 (.clk(clk), .ce(ce), .i(start), .o(d1));
150
delay4 #(1) ud3 (.clk(clk), .ce(ce), .i(d1), .o(done));
151
 
152
wire div_m_udf = div_m4[2*M+1];
153
wire [2*M+1:0] div_mN = ~div_m_udf ? div_m4 << 1'b1 : div_m4;
154
 
155
//Exponent and Regime Computation
156
wire bin = (~|sigb[M-2:0] | div_m_udf) ? 0 : 1;
157
wire [Bs+es+1:0] div_e = {argma, expa} - {argmb, expb} - bin;// 1 + ~|mant2 + div_m_udf;
158
wire [es-1:0] e_o = div_e[es-1:0];
159
wire [Bs+es:0] exp_oN = div_e[es+Bs+1] ? -div_e[es+Bs:0] : div_e[es+Bs:0];
160
wire [Bs:0] r_o = (~div_e[es+Bs+1] || |(exp_oN[es-1:0])) ? exp_oN[Bs+es:es] + 1 : exp_oN[es+Bs:es];
161
 
162
//Exponent and Mantissa Packing
163
wire [2*N-1+3:0] tmp_o = {{N{~div_e[es+Bs+1]}},div_e[es+Bs+1],e_o,div_mN[2*M:2*M-(N-es-1)+1], div_mN[2*M-(N-es-1):2*M-(N-es-1)-1],|div_mN[2*M-(N-es-1)-2:0] };
164
 
165
//Including Regime bits in Exponent-Mantissa Packing
166
wire [3*N-1+3:0] tmp1_o = {tmp_o,{N{1'b0}}} >> (r_o[Bs] ? {Bs{1'b1}} : r_o);
167
 
168
//Rounding RNE : ulp_add = G.(R + S) + L.G.(~(R+S))
169
wire L = tmp1_o[N+4], G = tmp1_o[N+3], R = tmp1_o[N+2], St = |tmp1_o[N+1:0],
170
     ulp = ((G & (R | St)) | (L & G & ~(R | St)));
171
wire [N-1:0] rnd_ulp = {{N-1{1'b0}},ulp};
172
 
173
wire [N:0] tmp1_o_rnd_ulp = tmp1_o[2*N-1+3:N+3] + rnd_ulp;
174
wire [N-1:0] tmp1_o_rnd = (r_o < M-2) ? tmp1_o_rnd_ulp[N-1:0] : tmp1_o[2*N-1+3:N+3];
175
 
176
//Final Output
177
wire [N-1:0] tmp1_oN = so ? -tmp1_o_rnd : tmp1_o_rnd;
178
assign o = inf|zero|(~div_mN[2*M+1]) ? {inf,{N-1{1'b0}}} : {so, tmp1_oN[N-1:1]};
179
 
180
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.