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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positFDP.sv] - Blame information for rev 66

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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      positFDP.v
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//    - posit number fused dot product
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//    - parameterized width
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//    - performs: a*b +/- c*d
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//
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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// ============================================================================
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import posit::*;
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module positFDP(op, a, b, c, d, o, zero, inf);
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input op;
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input [PSTWID-1:0] a;
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input [PSTWID-1:0] b;
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input [PSTWID-1:0] c;
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input [PSTWID-1:0] d;
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output [PSTWID-1:0] o;
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output zero;
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output inf;
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wire [PSTWID+es+(PSTWID-es)*2-1:0] o1;
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wire [PSTWID+es+(PSTWID-es)*2-1:0] o2;
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positFDPMul u1 (a, b, o1, zero1, inf1);
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positFDPMul u2 (c, d, o2, zero2, inf2);
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positFDPAddsub u3 (op, o1, o2, o, zero, inf);
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endmodule

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