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[/] [ft816float/] [trunk/] [rtl/] [positVerilog/] [positToInt.sv] - Blame information for rev 45

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1 45 robfinch
// ============================================================================
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//        __
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//   \\__/ o\    (C) 2020  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch@finitron.ca
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//       ||
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//
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//      positToInt.sv
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//    - posit number to integer convertor
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//    - can issue every clock cycle
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//    - parameterized width
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This source file is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program.  If not, see .
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//
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// ============================================================================
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`include "positConfig.sv"
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module positToInt(i, o);
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`include "positSize.sv"
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input [PSTWID-1:0] i;
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output reg [PSTWID-1:0] o;
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localparam N = PSTWID;
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localparam Bs = $clog2(PSTWID-1);
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wire sgn;
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wire rgs;
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wire [Bs-1:0] rgm;
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wire [es-1:0] exp;
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wire [N-es-1:0] sig;
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wire zer;
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wire inf;
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positDecompose #(.PSTWID(PSTWID), .es(es)) u1 (.i(i), .sgn(sgn), .rgs(rgs), .rgm(rgm), .exp(exp), .sig(sig), .zer(zer), .inf(inf));
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wire [N-1:0] m = {sig,{es{1'b0}}};
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// If we have a negative regime then the number is a fraction less than one (output a zero).
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wire isZero = zer|~rgs;
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wire [15:0] ex = (rgm << es) + exp;
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wire [N-1:0] mo = m >> (PSTWID-ex-1);
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always @*
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casez({isZero,inf})    // exponent all ones or exponent overflow?
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// convert to +0.0 zero-in zero-out (the sign will always be plus)
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2'b1?:  o = {PSTWID{1'b0}};
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// Infinity in or exponent overflow in conversion = infinity out
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2'b01:  o = {1'b1,{PSTWID-1{1'b0}}};
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// Other numbers
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default:  o = sgn ? -mo : mo;
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endcase
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endmodule

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