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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [DivGoldschmidt.v] - Blame information for rev 26

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1 14 robfinch
`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//      DivGoldschmidt.v
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//              
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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//
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// ============================================================================
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//
28 26 robfinch
module DivGoldschmidt(rst, clk, ld, a, b, q, done, lzcnt);
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parameter WID=32;
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parameter WHOLE=16;
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parameter POINTS=16;
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parameter LEFT=1'b1;
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localparam SIZE=WID+WHOLE;
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localparam POINTS2 = POINTS+WHOLE;
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input rst;
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input clk;
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input ld;
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input [WID-1:0] a;
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input [WID-1:0] b;
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output reg [WID*2-1:0] q;
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output reg done;
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output reg [7:0] lzcnt;
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parameter IDLE = 2'd0;
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parameter DIV = 2'd1;
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parameter DONE = 2'd2;
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parameter DIV2 = 2'd3;
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integer n;
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// Scale D so it is between 0 < D < 1 (shift)
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reg [SIZE-1:0] F;
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reg [SIZE*3-1:0] N, D;
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wire [SIZE*3-1:0] N1, D1;
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assign N1 = N * F;
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assign D1 = D * F;
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reg [1:0] state = IDLE;
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reg [7:0] count = 0;
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reg [7:0] lzcnt2;
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wire [7:0] shft;
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// Count the leading zeros on the b side input. Determines how much
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// shifting is required.
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always @*
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begin
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        lzcnt2 = 8'd0;
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        if (b[WID-1]==1'b0)
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                for (n = WID-2; n >= 0; n = n - 1)
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                        if(b[n] && lzcnt2==8'd0)
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                                lzcnt2 = (WID-1)-n;
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end
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// Count the leading zeros in the output. the float divider uses this.
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always @*
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begin
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        lzcnt = 8'd0;
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        if (q[WID*2-1]==1'b0)
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                for (n = WID*2-2; n >= 0; n = n - 1)
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                        if(q[n] && lzcnt==8'd0)
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                                lzcnt = (WID*2-1)-n;
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end
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wire shift_left = lzcnt2 > WHOLE;
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assign shft = shift_left ? lzcnt2-WHOLE : WHOLE-lzcnt2;
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//assign done = (state==IDLE && !ld)||state==DONE;
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always @(posedge clk)
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if (rst) begin
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        done <= 1'b0;
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        count <= 6'd0;
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        state <= IDLE;
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end
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else begin
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        done <= 1'b0;
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case(state)
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IDLE:
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        begin
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                if (ld) begin
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                        // Shifting the numerator and denomintor right or left using a barrel
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                        // or funnel shifter is what gives Goldschmidt a lot of it's performance.
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                        // Most of the divide is being performed by shifting.
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                        // For most floating point numbers shifting left isn't required as the
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                        // number is always between 1.0 and 2.0. Instead typically only a single
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                        // shift to the right is required. For fixed point numbers however, we
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                        // probably want to be able to shift left, hence the LEFT parameter.
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                        // With no left shifting the only impact is for denormal numbers which
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                        // take longer for the divide to converge.
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                        if (shift_left) begin
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                                if (LEFT) begin
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                                        N <= {16'd0,a,{WHOLE{1'b0}}} << shft;
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                                        D <= {16'd0,b,{WHOLE{1'd0}}} << shft;
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                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} << shft);
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                                end
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                                else begin
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                                        N <= {16'd0,a,{WHOLE{1'b0}}};
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                                        D <= {16'd0,b,{WHOLE{1'd0}}};
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                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}});
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                                end
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                        end
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                        else begin
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                                N <= {16'd0,a,{WHOLE{1'b0}}} >> shft;
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                                D <= {16'd0,b,{WHOLE{1'd0}}} >> shft;
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                                F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} >> shft);
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                        end
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                        count <= 0;
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                        state <= DIV;
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                end
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        end
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DIV:
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        begin
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                $display("C: %d N: %x D: %x F: %x", count, N,D,F);
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                N <= N1[SIZE*3-1:POINTS2] + N1[POINTS2-1];
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                D <= D1[SIZE*3-1:POINTS2] + D1[POINTS2-1];
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                F <= {16'd2,{POINTS2{1'd0}}} - (D1[SIZE*3-1:POINTS2] + D1[POINTS2-1]);
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//              q <= N1[SIZE*2-1:POINTS2] + N1[POINTS2-1];
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                if (D[SIZE*3-1:0]=={2'h1,{POINTS2{1'd0}}})
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                        state <= DONE;
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                count <= count + 1;
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        end
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DONE:
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        begin
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                done <= 1'b1;
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                q <= N[SIZE*3-1:0];
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                state <= IDLE;
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        end
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endcase
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end
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endmodule
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module G_divider_tb();
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parameter WID=4;
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reg rst;
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reg clk;
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reg ld;
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wire done;
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wire [WID*2-1:0] qo;
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reg [3:0] state;
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reg [3:0] a, b;
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reg [7:0] count;
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initial begin
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        clk = 1;
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        rst = 0;
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        #100 rst = 1;
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        #100 rst = 0;
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        #100 ld = 1;
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        #150 ld = 0;
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end
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always #10 clk = ~clk;  //  50 MHz
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always @(posedge clk)
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if (rst) begin
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        state <= 3'd0;
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        count = 0;
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end
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else begin
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case(state)
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3'd0:
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        begin
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                ld <= 1;
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                a <= count[7:4];
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                b <= count[3:0];
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        end
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3'd1:
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        if (done) begin
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                $display("C: %x Q: %x  f: %x", count, qo, f0);
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                state <= 3'd2;
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        end
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3'd2:
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        begin
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                count <= count + 8'd1;
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                state <= 3'd0;
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        end
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endcase
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end
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DivGoldschmidt #(.WID(WID),.WHOLE(1),.POINTS(3)) u00
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(
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        .rst(rst),
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        .clk(clk),
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        .ld(ld),
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//      .sgn(1'b1),
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//      .isDivi(1'b0),
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        .a(a),
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        .b(b),
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//      .imm(64'd123),
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        .q(qo),
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//      .ro(ro),
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//      .dvByZr(),
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        .done(done),
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        .lzcnt()
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);
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endmodule
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