OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] [DivGoldschmidt.v] - Blame information for rev 89

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 14 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2017-2018  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch<remove>@finitron.ca
7
//       ||
8
//
9
//      DivGoldschmidt.v
10
//              
11
//
12
// This source file is free software: you can redistribute it and/or modify 
13
// it under the terms of the GNU Lesser General Public License as published 
14
// by the Free Software Foundation, either version 3 of the License, or     
15
// (at your option) any later version.                                      
16
//                                                                          
17
// This source file is distributed in the hope that it will be useful,      
18
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
19
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
20
// GNU General Public License for more details.                             
21
//                                                                          
22
// You should have received a copy of the GNU General Public License        
23
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
24
//                                                                          
25
//
26
// ============================================================================
27
//
28 26 robfinch
module DivGoldschmidt(rst, clk, ld, a, b, q, done, lzcnt);
29 14 robfinch
parameter WID=32;
30
parameter WHOLE=16;
31
parameter POINTS=16;
32
parameter LEFT=1'b1;
33
localparam SIZE=WID+WHOLE;
34
localparam POINTS2 = POINTS+WHOLE;
35
input rst;
36
input clk;
37
input ld;
38
input [WID-1:0] a;
39
input [WID-1:0] b;
40
output reg [WID*2-1:0] q;
41
output reg done;
42
output reg [7:0] lzcnt;
43
parameter IDLE = 2'd0;
44
parameter DIV = 2'd1;
45
parameter DONE = 2'd2;
46
parameter DIV2 = 2'd3;
47
 
48
integer n;
49
// Scale D so it is between 0 < D < 1 (shift)
50
reg [SIZE-1:0] F;
51
reg [SIZE*3-1:0] N, D;
52
wire [SIZE*3-1:0] N1, D1;
53
assign N1 = N * F;
54
assign D1 = D * F;
55
reg [1:0] state = IDLE;
56
reg [7:0] count = 0;
57
reg [7:0] lzcnt2;
58
wire [7:0] shft;
59
 
60
// Count the leading zeros on the b side input. Determines how much
61
// shifting is required.
62
always @*
63
begin
64
        lzcnt2 = 8'd0;
65
        if (b[WID-1]==1'b0)
66
                for (n = WID-2; n >= 0; n = n - 1)
67
                        if(b[n] && lzcnt2==8'd0)
68
                                lzcnt2 = (WID-1)-n;
69
end
70
 
71
 
72
// Count the leading zeros in the output. the float divider uses this.
73
always @*
74
begin
75
        lzcnt = 8'd0;
76
        if (q[WID*2-1]==1'b0)
77
                for (n = WID*2-2; n >= 0; n = n - 1)
78
                        if(q[n] && lzcnt==8'd0)
79
                                lzcnt = (WID*2-1)-n;
80
end
81
 
82
wire shift_left = lzcnt2 > WHOLE;
83
assign shft = shift_left ? lzcnt2-WHOLE : WHOLE-lzcnt2;
84
//assign done = (state==IDLE && !ld)||state==DONE;
85
 
86
always @(posedge clk)
87
if (rst) begin
88
        done <= 1'b0;
89
        count <= 6'd0;
90
        state <= IDLE;
91
end
92
else begin
93
        done <= 1'b0;
94
case(state)
95
IDLE:
96
        begin
97
                if (ld) begin
98
                        // Shifting the numerator and denomintor right or left using a barrel
99
                        // or funnel shifter is what gives Goldschmidt a lot of it's performance.
100
                        // Most of the divide is being performed by shifting.
101
                        // For most floating point numbers shifting left isn't required as the
102
                        // number is always between 1.0 and 2.0. Instead typically only a single
103
                        // shift to the right is required. For fixed point numbers however, we
104
                        // probably want to be able to shift left, hence the LEFT parameter.
105
                        // With no left shifting the only impact is for denormal numbers which
106
                        // take longer for the divide to converge.
107
                        if (shift_left) begin
108
                                if (LEFT) begin
109
                                        N <= {16'd0,a,{WHOLE{1'b0}}} << shft;
110
                                        D <= {16'd0,b,{WHOLE{1'd0}}} << shft;
111
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} << shft);
112
                                end
113
                                else begin
114
                                        N <= {16'd0,a,{WHOLE{1'b0}}};
115
                                        D <= {16'd0,b,{WHOLE{1'd0}}};
116
                                        F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}});
117
                                end
118
                        end
119
                        else begin
120
                                N <= {16'd0,a,{WHOLE{1'b0}}} >> shft;
121
                                D <= {16'd0,b,{WHOLE{1'd0}}} >> shft;
122
                                F <= {16'd2,{POINTS2{1'b0}}} - ({b,{WHOLE{1'd0}}} >> shft);
123
                        end
124
                        count <= 0;
125
                        state <= DIV;
126
                end
127
        end
128
DIV:
129
        begin
130
                $display("C: %d N: %x D: %x F: %x", count, N,D,F);
131
                N <= N1[SIZE*3-1:POINTS2] + N1[POINTS2-1];
132
                D <= D1[SIZE*3-1:POINTS2] + D1[POINTS2-1];
133
                F <= {16'd2,{POINTS2{1'd0}}} - (D1[SIZE*3-1:POINTS2] + D1[POINTS2-1]);
134
//              q <= N1[SIZE*2-1:POINTS2] + N1[POINTS2-1];
135
                if (D[SIZE*3-1:0]=={2'h1,{POINTS2{1'd0}}})
136
                        state <= DONE;
137
                count <= count + 1;
138
        end
139
DONE:
140
        begin
141
                done <= 1'b1;
142
                q <= N[SIZE*3-1:0];
143
                state <= IDLE;
144
        end
145
endcase
146
end
147
 
148
endmodule
149
 
150
module G_divider_tb();
151
parameter WID=4;
152
reg rst;
153
reg clk;
154
reg ld;
155
wire done;
156
wire [WID*2-1:0] qo;
157
reg [3:0] state;
158
reg [3:0] a, b;
159
reg [7:0] count;
160
 
161
initial begin
162
        clk = 1;
163
        rst = 0;
164
        #100 rst = 1;
165
        #100 rst = 0;
166
        #100 ld = 1;
167
        #150 ld = 0;
168
end
169
 
170
always #10 clk = ~clk;  //  50 MHz
171
 
172
always @(posedge clk)
173
if (rst) begin
174
        state <= 3'd0;
175
        count = 0;
176
end
177
else begin
178
case(state)
179
3'd0:
180
        begin
181
                ld <= 1;
182
                a <= count[7:4];
183
                b <= count[3:0];
184
        end
185
3'd1:
186
        if (done) begin
187
                $display("C: %x Q: %x  f: %x", count, qo, f0);
188
                state <= 3'd2;
189
        end
190
3'd2:
191
        begin
192
                count <= count + 8'd1;
193
                state <= 3'd0;
194
        end
195
endcase
196
end
197
 
198
DivGoldschmidt #(.WID(WID),.WHOLE(1),.POINTS(3)) u00
199
(
200
        .rst(rst),
201
        .clk(clk),
202
        .ld(ld),
203
//      .sgn(1'b1),
204
//      .isDivi(1'b0),
205
        .a(a),
206
        .b(b),
207
//      .imm(64'd123),
208
        .q(qo),
209
//      .ro(ro),
210
//      .dvByZr(),
211 26 robfinch
        .done(done),
212
        .lzcnt()
213 14 robfinch
);
214
 
215
endmodule
216
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.