OpenCores
URL https://opencores.org/ocsvn/ft816float/ft816float/trunk

Subversion Repositories ft816float

[/] [ft816float/] [trunk/] [rtl/] [verilog/] [F32ToF80.v] - Blame information for rev 63

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 16 robfinch
`timescale 1ns / 1ps
2
// ============================================================================
3
//        __
4
//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
5
//    \  __ /    All rights reserved.
6
//     \/_//     robfinch<remove>@finitron.ca
7
//       ||
8
//
9
//
10
//
11
// This source file is free software: you can redistribute it and/or modify 
12
// it under the terms of the GNU Lesser General Public License as published 
13
// by the Free Software Foundation, either version 3 of the License, or     
14
// (at your option) any later version.                                      
15
//                                                                          
16
// This source file is distributed in the hope that it will be useful,      
17
// but WITHOUT ANY WARRANTY; without even the implied warranty of           
18
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
19
// GNU General Public License for more details.                             
20
//                                                                          
21
// You should have received a copy of the GNU General Public License        
22
// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
23
//                                                                          
24
// ============================================================================
25
 
26
module F32ToF80(a, o);
27
input [31:0] a;
28
output [79:0] o;
29
 
30
reg signo;
31
reg [14:0] expo;
32
reg [63:0] mano;
33
 
34
assign o = {signo,expo,mano};
35
 
36
wire signi;
37
wire [7:0] expi;
38
wire [22:0] mani;
39
wire xinf;      // exponent infinite
40
wire vz;        // value zero
41
wire xz;        // exponent zero
42
 
43
fpDecomp #(32) u1 (.i(a), .sgn(signi), .exp(expi), .man(mani), .xinf(xinf), .xz(xz), .vz(vz) );
44
wire [5:0] lz;
45
cntlz32 u2 ({mani,9'b111111111}, lz);   // '1' bit already unhidden due to denormalized number
46
 
47
always @*
48
begin
49
  // sign out always just = sign in
50 26 robfinch
  signo <= signi;
51 16 robfinch
 
52
  // special check for zero
53
  if (vz) begin
54 26 robfinch
    expo <= 1'd0;
55
    mano <= 1'd0;
56 16 robfinch
  end
57
  // convert infinity / nan
58
  // infinity in = infinity out
59
  else if (xinf) begin
60
    expo <= 15'h7fff;
61
    mano <= {mani,41'b0};
62
  end
63
  // convert denormal
64
  // a denormal was really a number with an exponent of -126
65
  // this value is easily represented in the double format
66
  // it may be possible to normalize the value if it isn't
67
  // zero
68
  else if (xz) begin
69
    expo <= 15'h3fff - 8'h7e - lz;      // 32767 "zero" -1022 - lz
70
    mano <= {mani << (lz + 1), 41'd0};  // shift one more to hide leading '1'
71
  end
72
  // convert typical number
73
  // adjust exponent, copy mantissa
74
  else begin
75
    expo <= expi + 15'h3fff - 8'h7f;
76
    mano <= {mani,41'd0};
77
  end
78
end
79
 
80
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.