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[/] [ft816float/] [trunk/] [rtl/] [verilog/] [F32ToF80.v] - Blame information for rev 85

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`timescale 1ns / 1ps
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// ============================================================================
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//        __
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//   \\__/ o\    (C) 2006-2019  Robert Finch, Waterloo
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//    \  __ /    All rights reserved.
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//     \/_//     robfinch<remove>@finitron.ca
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//       ||
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//
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//
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//
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// This source file is free software: you can redistribute it and/or modify 
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// it under the terms of the GNU Lesser General Public License as published 
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// by the Free Software Foundation, either version 3 of the License, or     
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// (at your option) any later version.                                      
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//                                                                          
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// This source file is distributed in the hope that it will be useful,      
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// but WITHOUT ANY WARRANTY; without even the implied warranty of           
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            
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// GNU General Public License for more details.                             
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//                                                                          
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// You should have received a copy of the GNU General Public License        
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// along with this program.  If not, see <http://www.gnu.org/licenses/>.    
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//                                                                          
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// ============================================================================
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module F32ToF80(a, o);
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input [31:0] a;
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output [79:0] o;
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reg signo;
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reg [14:0] expo;
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reg [63:0] mano;
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assign o = {signo,expo,mano};
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wire signi;
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wire [7:0] expi;
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wire [22:0] mani;
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wire xinf;      // exponent infinite
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wire vz;        // value zero
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wire xz;        // exponent zero
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fpDecomp #(32) u1 (.i(a), .sgn(signi), .exp(expi), .man(mani), .xinf(xinf), .xz(xz), .vz(vz) );
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wire [5:0] lz;
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cntlz32 u2 ({mani,9'b111111111}, lz);   // '1' bit already unhidden due to denormalized number
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always @*
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begin
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  // sign out always just = sign in
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  signo <= signi;
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  // special check for zero
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  if (vz) begin
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    expo <= 1'd0;
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    mano <= 1'd0;
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  end
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  // convert infinity / nan
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  // infinity in = infinity out
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  else if (xinf) begin
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    expo <= 15'h7fff;
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    mano <= {mani,41'b0};
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  end
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  // convert denormal
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  // a denormal was really a number with an exponent of -126
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  // this value is easily represented in the double format
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  // it may be possible to normalize the value if it isn't
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  // zero
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  else if (xz) begin
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    expo <= 15'h3fff - 8'h7e - lz;      // 32767 "zero" -1022 - lz
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    mano <= {mani << (lz + 1), 41'd0};  // shift one more to hide leading '1'
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  end
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  // convert typical number
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  // adjust exponent, copy mantissa
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  else begin
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    expo <= expi + 15'h3fff - 8'h7f;
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    mano <= {mani,41'd0};
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  end
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end
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endmodule

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